Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3576436	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4318110

1

T1

10891

T2

10580

T3

6596

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4399970	1			T1	4102		T2	1695		T3	7739
values[0x0]	1745890	1			T1	4442		T2	4853		T3	3166
values[0x1]	1748686	1			T1	4362		T2	4819		T3	3114

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2547311	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5347235

1

T1

11329

T2

10761

T3

8947

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28323	1			T1	53		T2	49		T3	43
valid_sources[0x01]	28580	1			T1	62		T2	31		T3	59
valid_sources[0x02]	33863	1			T1	44		T2	55		T3	48
valid_sources[0x03]	32885	1			T1	40		T2	58		T3	60
valid_sources[0x04]	30152	1			T1	49		T2	68		T3	51
valid_sources[0x05]	32605	1			T1	57		T2	52		T3	57
valid_sources[0x06]	29289	1			T1	67		T2	29		T3	40
valid_sources[0x07]	29228	1			T1	52		T2	35		T3	56
valid_sources[0x08]	28044	1			T1	55		T2	35		T3	48
valid_sources[0x09]	27387	1			T1	61		T2	55		T3	51
valid_sources[0x0a]	31848	1			T1	51		T2	30		T3	62
valid_sources[0x0b]	28988	1			T1	47		T2	48		T3	66
valid_sources[0x0c]	28427	1			T1	56		T2	38		T3	70
valid_sources[0x0d]	29132	1			T1	58		T2	29		T3	56
valid_sources[0x0e]	27630	1			T1	59		T2	15		T3	43
valid_sources[0x0f]	29344	1			T1	37		T2	87		T3	55
valid_sources[0x10]	31106	1			T1	34		T2	65		T3	47
valid_sources[0x11]	31324	1			T1	61		T2	20		T3	58
valid_sources[0x12]	29066	1			T1	46		T2	60		T3	48
valid_sources[0x13]	28389	1			T1	56		T2	28		T3	46
valid_sources[0x14]	27388	1			T1	50		T2	66		T3	59
valid_sources[0x15]	36495	1			T1	37		T2	55		T3	64
valid_sources[0x16]	42010	1			T1	36		T2	53		T3	66
valid_sources[0x17]	54779	1			T1	51		T2	27		T3	53
valid_sources[0x18]	29248	1			T1	54		T2	42		T3	48
valid_sources[0x19]	61594	1			T1	34		T2	46		T3	66
valid_sources[0x1a]	33263	1			T1	43		T2	48		T3	59
valid_sources[0x1b]	32324	1			T1	53		T2	40		T3	41
valid_sources[0x1c]	31152	1			T1	35		T2	15		T3	60
valid_sources[0x1d]	32177	1			T1	50		T2	22		T3	66
valid_sources[0x1e]	29944	1			T1	56		T2	40		T3	55
valid_sources[0x1f]	26978	1			T1	45		T2	49		T3	48
valid_sources[0x20]	28562	1			T1	48		T2	111		T3	43
valid_sources[0x21]	28004	1			T1	56		T2	56		T3	45
valid_sources[0x22]	27408	1			T1	53		T2	62		T3	49
valid_sources[0x23]	30783	1			T1	61		T2	57		T3	55
valid_sources[0x24]	29168	1			T1	54		T2	38		T3	58
valid_sources[0x25]	27207	1			T1	40		T2	59		T3	42
valid_sources[0x26]	30047	1			T1	44		T2	63		T3	56
valid_sources[0x27]	28433	1			T1	58		T2	29		T3	53
valid_sources[0x28]	32264	1			T1	47		T2	39		T3	59
valid_sources[0x29]	29986	1			T1	41		T2	18		T3	56
valid_sources[0x2a]	28105	1			T1	63		T2	43		T3	58
valid_sources[0x2b]	26728	1			T1	39		T2	46		T3	57
valid_sources[0x2c]	30687	1			T1	52		T2	50		T3	59
valid_sources[0x2d]	28985	1			T1	53		T2	51		T3	51
valid_sources[0x2e]	32534	1			T1	62		T2	25		T3	53
valid_sources[0x2f]	28186	1			T1	63		T2	45		T3	61
valid_sources[0x30]	28224	1			T1	54		T2	30		T3	51
valid_sources[0x31]	29720	1			T1	44		T2	55		T3	65
valid_sources[0x32]	31985	1			T1	47		T2	22		T3	57
valid_sources[0x33]	29781	1			T1	65		T2	43		T3	52
valid_sources[0x34]	37697	1			T1	60		T2	18		T3	58
valid_sources[0x35]	27849	1			T1	40		T2	63		T3	63
valid_sources[0x36]	29186	1			T1	52		T2	46		T3	65
valid_sources[0x37]	28050	1			T1	46		T2	57		T3	61
valid_sources[0x38]	29450	1			T1	62		T2	50		T3	52
valid_sources[0x39]	28622	1			T1	58		T2	97		T3	48
valid_sources[0x3a]	27119	1			T1	60		T2	57		T3	72
valid_sources[0x3b]	28464	1			T1	60		T2	26		T3	47
valid_sources[0x3c]	28325	1			T1	65		T2	50		T3	45
valid_sources[0x3d]	27628	1			T1	68		T2	38		T3	55
valid_sources[0x3e]	29648	1			T1	55		T2	19		T3	66
valid_sources[0x3f]	30231	1			T1	40		T2	22		T3	54
valid_sources[0x40]	27362	1			T1	37		T2	43		T3	46
valid_sources[0x41]	25976	1			T1	36		T2	29		T3	50
valid_sources[0x42]	27371	1			T1	60		T2	45		T3	71
valid_sources[0x43]	27552	1			T1	54		T2	88		T3	56
valid_sources[0x44]	35122	1			T1	47		T2	20		T3	42
valid_sources[0x45]	27432	1			T1	40		T2	27		T3	48
valid_sources[0x46]	28356	1			T1	37		T2	73		T3	47
valid_sources[0x47]	32744	1			T1	45		T2	57		T3	54
valid_sources[0x48]	30749	1			T1	57		T2	33		T3	51
valid_sources[0x49]	27303	1			T1	43		T2	36		T3	60
valid_sources[0x4a]	29368	1			T1	54		T2	48		T3	57
valid_sources[0x4b]	28839	1			T1	49		T2	50		T3	49
valid_sources[0x4c]	29407	1			T1	51		T2	23		T3	43
valid_sources[0x4d]	28875	1			T1	49		T2	56		T3	49
valid_sources[0x4e]	35571	1			T1	44		T2	36		T3	60
valid_sources[0x4f]	30914	1			T1	54		T2	36		T3	58
valid_sources[0x50]	28096	1			T1	66		T2	27		T3	51
valid_sources[0x51]	28196	1			T1	51		T2	44		T3	42
valid_sources[0x52]	27543	1			T1	51		T2	45		T3	52
valid_sources[0x53]	28781	1			T1	46		T2	28		T3	60
valid_sources[0x54]	28888	1			T1	46		T2	47		T3	50
valid_sources[0x55]	28444	1			T1	46		T2	28		T3	60
valid_sources[0x56]	28863	1			T1	52		T2	37		T3	49
valid_sources[0x57]	28591	1			T1	28		T2	37		T3	50
valid_sources[0x58]	27160	1			T1	55		T2	52		T3	52
valid_sources[0x59]	27480	1			T1	44		T2	28		T3	57
valid_sources[0x5a]	29020	1			T1	50		T2	23		T3	47
valid_sources[0x5b]	30045	1			T1	52		T2	24		T3	59
valid_sources[0x5c]	27869	1			T1	72		T2	32		T3	47
valid_sources[0x5d]	27947	1			T1	45		T2	51		T3	58
valid_sources[0x5e]	41191	1			T1	46		T2	44		T3	58
valid_sources[0x5f]	28613	1			T1	33		T2	34		T3	51
valid_sources[0x60]	28113	1			T1	56		T2	28		T3	66
valid_sources[0x61]	31132	1			T1	56		T2	44		T3	53
valid_sources[0x62]	28765	1			T1	54		T2	64		T3	51
valid_sources[0x63]	28827	1			T1	42		T2	39		T3	53
valid_sources[0x64]	29968	1			T1	55		T2	51		T3	32
valid_sources[0x65]	32336	1			T1	55		T2	77		T3	46
valid_sources[0x66]	29784	1			T1	49		T2	47		T3	52
valid_sources[0x67]	28527	1			T1	56		T2	66		T3	71
valid_sources[0x68]	31404	1			T1	66		T2	43		T3	52
valid_sources[0x69]	28904	1			T1	41		T2	17		T3	45
valid_sources[0x6a]	31215	1			T1	48		T2	45		T3	57
valid_sources[0x6b]	28734	1			T1	52		T2	25		T3	56
valid_sources[0x6c]	28979	1			T1	46		T2	22		T3	56
valid_sources[0x6d]	26689	1			T1	57		T2	14		T3	56
valid_sources[0x6e]	28548	1			T1	48		T2	53		T3	56
valid_sources[0x6f]	30517	1			T1	54		T2	43		T3	58
valid_sources[0x70]	27350	1			T1	47		T2	43		T3	61
valid_sources[0x71]	37984	1			T1	48		T2	48		T3	54
valid_sources[0x72]	29799	1			T1	33		T2	79		T3	60
valid_sources[0x73]	27683	1			T1	46		T2	59		T3	48
valid_sources[0x74]	28200	1			T1	58		T2	41		T3	43
valid_sources[0x75]	29343	1			T1	56		T2	77		T3	44
valid_sources[0x76]	41322	1			T1	43		T2	45		T3	54
valid_sources[0x77]	31002	1			T1	57		T2	25		T3	54
valid_sources[0x78]	31281	1			T1	42		T2	39		T3	44
valid_sources[0x79]	30352	1			T1	42		T2	54		T3	60
valid_sources[0x7a]	29232	1			T1	52		T2	51		T3	60
valid_sources[0x7b]	29159	1			T1	62		T2	62		T3	54
valid_sources[0x7c]	29541	1			T1	55		T2	33		T3	61
valid_sources[0x7d]	28032	1			T1	47		T2	60		T3	62
valid_sources[0x7e]	31602	1			T1	46		T2	33		T3	54
valid_sources[0x7f]	41661	1			T1	58		T2	88		T3	66
valid_sources[0x80]	30852	1			T1	47		T2	25		T3	56

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1143106

1

T1

2136

T2

947

T3

1037

values[0x0]

all_enables

biggest_size

1598440

1

T1

4429

T2

4842

T3

2801

values[0x1]

all_enables

biggest_size

1576564

1

T1

4326

T2

4791

T3

2758