Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3601592

1

T1

2015

T2

787

T3

7423

full_word

4317391

1

T1

10891

T2

10580

T3

6596

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7918593	1			T1	12906		T2	11367		T3	14019
auto[TlIntgErrCmd]	142	1			T83	14		T84	2		T85	6
auto[TlIntgErrData]	106	1			T83	7		T84	2		T85	9
auto[TlIntgErrBoth]	142	1			T83	9		T84	6		T85	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4403526

1

T1

4102

T2

1695

T3

7739

auto[1]

3515457

1

T1

8804

T2

9672

T3

6280

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3260041	1			T1	1966		T2	748		T3	6702
auto[TlIntgErrNone]	partial	auto[1]	341192	1			T1	49		T2	39		T3	721
auto[TlIntgErrNone]	full_word	auto[0]	1143305	1			T1	2136		T2	947		T3	1037
auto[TlIntgErrNone]	full_word	auto[1]	3174055	1			T1	8755		T2	9633		T3	5559
auto[TlIntgErrCmd]	partial	auto[0]	53	1			T83	6		T84	1		T85	1
auto[TlIntgErrCmd]	partial	auto[1]	77	1			T83	6		T84	1		T85	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T162	1		T164	1		T165	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T83	2		T165	2		T166	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T83	3		T84	2		T85	2
auto[TlIntgErrData]	partial	auto[1]	47	1			T83	3		T85	7		T162	3
auto[TlIntgErrData]	full_word	auto[0]	1	1			T167	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T83	1		T163	1		T168	1
auto[TlIntgErrBoth]	partial	auto[0]	65	1			T83	3		T84	2		T85	2
auto[TlIntgErrBoth]	partial	auto[1]	66	1			T83	6		T84	4		T85	3
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T163	1		T169	1		T170	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T162	1		T166	1		T171	1