Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	469182393	2930115	0	0
DepthKnown_A	469182393	469050697	0	0
RvalidKnown_A	469182393	469050697	0	0
WreadyKnown_A	469182393	469050697	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469182393	2930115	0	0
T1	236856	9982	0	0
T2	855680	15809	0	0
T3	911280	3327	0	0
T4	105785	11661	0	0
T5	16321	2696	0	0
T6	179455	9148	0	0
T7	62007	1663	0	0
T8	8415	3394	0	0
T9	180282	1663	0	0
T10	2695	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469182393	469050697	0	0
T1	236856	236851	0	0
T2	855680	855614	0	0
T3	911280	911064	0	0
T4	105785	105775	0	0
T5	16321	16257	0	0
T6	179455	179446	0	0
T7	62007	61948	0	0
T8	8415	8357	0	0
T9	180282	180226	0	0
T10	2695	2598	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469182393	469050697	0	0
T1	236856	236851	0	0
T2	855680	855614	0	0
T3	911280	911064	0	0
T4	105785	105775	0	0
T5	16321	16257	0	0
T6	179455	179446	0	0
T7	62007	61948	0	0
T8	8415	8357	0	0
T9	180282	180226	0	0
T10	2695	2598	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469182393	469050697	0	0
T1	236856	236851	0	0
T2	855680	855614	0	0
T3	911280	911064	0	0
T4	105785	105775	0	0
T5	16321	16257	0	0
T6	179455	179446	0	0
T7	62007	61948	0	0
T8	8415	8357	0	0
T9	180282	180226	0	0
T10	2695	2598	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	469182393	3224709	0	0
DepthKnown_A	469182393	469050697	0	0
RvalidKnown_A	469182393	469050697	0	0
WreadyKnown_A	469182393	469050697	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469182393	3224709	0	0
T1	236856	8320	0	0
T2	855680	14542	0	0
T3	911280	2496	0	0
T4	105785	25867	0	0
T5	16321	1355	0	0
T6	179455	5824	0	0
T7	62007	832	0	0
T8	8415	2119	0	0
T9	180282	832	0	0
T10	2695	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469182393	469050697	0	0
T1	236856	236851	0	0
T2	855680	855614	0	0
T3	911280	911064	0	0
T4	105785	105775	0	0
T5	16321	16257	0	0
T6	179455	179446	0	0
T7	62007	61948	0	0
T8	8415	8357	0	0
T9	180282	180226	0	0
T10	2695	2598	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469182393	469050697	0	0
T1	236856	236851	0	0
T2	855680	855614	0	0
T3	911280	911064	0	0
T4	105785	105775	0	0
T5	16321	16257	0	0
T6	179455	179446	0	0
T7	62007	61948	0	0
T8	8415	8357	0	0
T9	180282	180226	0	0
T10	2695	2598	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469182393	469050697	0	0
T1	236856	236851	0	0
T2	855680	855614	0	0
T3	911280	911064	0	0
T4	105785	105775	0	0
T5	16321	16257	0	0
T6	179455	179446	0	0
T7	62007	61948	0	0
T8	8415	8357	0	0
T9	180282	180226	0	0
T10	2695	2598	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	469182393	191383	0	0
DepthKnown_A	469182393	469050697	0	0
RvalidKnown_A	469182393	469050697	0	0
WreadyKnown_A	469182393	469050697	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469182393	191383	0	0
T1	236856	270	0	0
T2	855680	257	0	0
T3	911280	309	0	0
T4	105785	762	0	0
T5	16321	0	0	0
T6	179455	258	0	0
T7	62007	0	0	0
T8	8415	0	0	0
T9	180282	0	0	0
T10	2695	100	0	0
T11	0	412	0	0
T13	0	635	0	0
T25	0	979	0	0
T34	0	292	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469182393	469050697	0	0
T1	236856	236851	0	0
T2	855680	855614	0	0
T3	911280	911064	0	0
T4	105785	105775	0	0
T5	16321	16257	0	0
T6	179455	179446	0	0
T7	62007	61948	0	0
T8	8415	8357	0	0
T9	180282	180226	0	0
T10	2695	2598	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469182393	469050697	0	0
T1	236856	236851	0	0
T2	855680	855614	0	0
T3	911280	911064	0	0
T4	105785	105775	0	0
T5	16321	16257	0	0
T6	179455	179446	0	0
T7	62007	61948	0	0
T8	8415	8357	0	0
T9	180282	180226	0	0
T10	2695	2598	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469182393	469050697	0	0
T1	236856	236851	0	0
T2	855680	855614	0	0
T3	911280	911064	0	0
T4	105785	105775	0	0
T5	16321	16257	0	0
T6	179455	179446	0	0
T7	62007	61948	0	0
T8	8415	8357	0	0
T9	180282	180226	0	0
T10	2695	2598	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	469182393	426152	0	0
DepthKnown_A	469182393	469050697	0	0
RvalidKnown_A	469182393	469050697	0	0
WreadyKnown_A	469182393	469050697	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469182393	426152	0	0
T1	236856	270	0	0
T2	855680	779	0	0
T3	911280	309	0	0
T4	105785	3421	0	0
T5	16321	0	0	0
T6	179455	258	0	0
T7	62007	0	0	0
T8	8415	0	0	0
T9	180282	0	0	0
T10	2695	100	0	0
T11	0	1859	0	0
T13	0	635	0	0
T25	0	4569	0	0
T34	0	292	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469182393	469050697	0	0
T1	236856	236851	0	0
T2	855680	855614	0	0
T3	911280	911064	0	0
T4	105785	105775	0	0
T5	16321	16257	0	0
T6	179455	179446	0	0
T7	62007	61948	0	0
T8	8415	8357	0	0
T9	180282	180226	0	0
T10	2695	2598	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469182393	469050697	0	0
T1	236856	236851	0	0
T2	855680	855614	0	0
T3	911280	911064	0	0
T4	105785	105775	0	0
T5	16321	16257	0	0
T6	179455	179446	0	0
T7	62007	61948	0	0
T8	8415	8357	0	0
T9	180282	180226	0	0
T10	2695	2598	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469182393	469050697	0	0
T1	236856	236851	0	0
T2	855680	855614	0	0
T3	911280	911064	0	0
T4	105785	105775	0	0
T5	16321	16257	0	0
T6	179455	179446	0	0
T7	62007	61948	0	0
T8	8415	8357	0	0
T9	180282	180226	0	0
T10	2695	2598	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	469182393	6198960	0	0
DepthKnown_A	469182393	469050697	0	0
RvalidKnown_A	469182393	469050697	0	0
WreadyKnown_A	469182393	469050697	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469182393	6198960	0	0
T1	236856	4322	0	0
T2	855680	1982	0	0
T3	911280	11338	0	0
T4	105785	2236	0	0
T5	16321	314	0	0
T6	179455	14906	0	0
T7	62007	1944	0	0
T8	8415	166	0	0
T9	180282	1611	0	0
T10	2695	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469182393	469050697	0	0
T1	236856	236851	0	0
T2	855680	855614	0	0
T3	911280	911064	0	0
T4	105785	105775	0	0
T5	16321	16257	0	0
T6	179455	179446	0	0
T7	62007	61948	0	0
T8	8415	8357	0	0
T9	180282	180226	0	0
T10	2695	2598	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469182393	469050697	0	0
T1	236856	236851	0	0
T2	855680	855614	0	0
T3	911280	911064	0	0
T4	105785	105775	0	0
T5	16321	16257	0	0
T6	179455	179446	0	0
T7	62007	61948	0	0
T8	8415	8357	0	0
T9	180282	180226	0	0
T10	2695	2598	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469182393	469050697	0	0
T1	236856	236851	0	0
T2	855680	855614	0	0
T3	911280	911064	0	0
T4	105785	105775	0	0
T5	16321	16257	0	0
T6	179455	179446	0	0
T7	62007	61948	0	0
T8	8415	8357	0	0
T9	180282	180226	0	0
T10	2695	2598	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	469182393	12619225	0	0
DepthKnown_A	469182393	469050697	0	0
RvalidKnown_A	469182393	469050697	0	0
WreadyKnown_A	469182393	469050697	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469182393	12619225	0	0
T1	236856	4316	0	0
T2	855680	5883	0	0
T3	911280	11214	0	0
T4	105785	9822	0	0
T5	16321	1260	0	0
T6	179455	14834	0	0
T7	62007	1944	0	0
T8	8415	287	0	0
T9	180282	7138	0	0
T10	2695	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469182393	469050697	0	0
T1	236856	236851	0	0
T2	855680	855614	0	0
T3	911280	911064	0	0
T4	105785	105775	0	0
T5	16321	16257	0	0
T6	179455	179446	0	0
T7	62007	61948	0	0
T8	8415	8357	0	0
T9	180282	180226	0	0
T10	2695	2598	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469182393	469050697	0	0
T1	236856	236851	0	0
T2	855680	855614	0	0
T3	911280	911064	0	0
T4	105785	105775	0	0
T5	16321	16257	0	0
T6	179455	179446	0	0
T7	62007	61948	0	0
T8	8415	8357	0	0
T9	180282	180226	0	0
T10	2695	2598	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469182393	469050697	0	0
T1	236856	236851	0	0
T2	855680	855614	0	0
T3	911280	911064	0	0
T4	105785	105775	0	0
T5	16321	16257	0	0
T6	179455	179446	0	0
T7	62007	61948	0	0
T8	8415	8357	0	0
T9	180282	180226	0	0
T10	2695	2598	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0