Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.05	100.00	85.19			100.00	75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
90.97	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T11
1	0	Covered	T3,T6,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T11
1	0	Unreachable
1	1	Covered	T3,T6,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	769779518	617048053	0	0
CheckNGreaterZero_A	2922	2922	0	0
GntImpliesReady_A	769779518	3650029	0	0
GntImpliesValid_A	769779518	3650029	0	0
GrantKnown_A	769779518	617048053	0	0
IdxKnown_A	769779518	617048053	0	0
IndexIsCorrect_A	769779518	3650029	0	0
LockArbDecision_A	769779518	0	0	0
NoReadyValidNoGrant_A	769779518	0	0	0
ReadyAndValidImplyGrant_A	769779518	3650029	0	0
ReqAndReadyImplyGrant_A	769779518	3650029	0	0
ReqImpliesValid_A	769779518	3650029	0	0
ReqStaysHighUntilGranted0_M	769779518	0	0	0
RoundRobin_A	769779518	0	0	974
ValidKnown_A	769779518	617048053	0	0
gen_data_port_assertion.DataFlow_A	769779518	3650029	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769779518	617048053	0	0
T1	699443	697611	0	0
T2	1648957	1646015	0	0
T3	1502644	1205681	0	0
T4	750267	424821	0	0
T5	119939	68066	0	0
T6	1070757	622112	0	0
T7	100363	80958	0	0
T8	49475	28887	0	0
T9	224496	202333	0	0
T10	2695	2598	0	0
T11	1308180	650513	0	0
T12	96891	93120	0	0
T13	0	132936	0	0
T14	0	678168	0	0
T24	0	104136	0	0
T25	0	74464	0	0
T26	0	14096	0	0
T27	0	22040	0	0
T35	182696	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2922	2922	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769779518	3650029	0	0
T1	699443	13182	0	0
T2	1648957	14797	0	0
T3	1502644	10542	0	0
T4	750267	13336	0	0
T5	119939	1344	0	0
T6	1070757	9175	0	0
T7	100363	832	0	0
T8	49475	2112	0	0
T9	224496	832	0	0
T10	2695	200	0	0
T11	1308180	3060	0	0
T12	96891	0	0	0
T13	0	3631	0	0
T14	0	9026	0	0
T25	0	13534	0	0
T26	0	8928	0	0
T27	0	7694	0	0
T34	0	1714	0	0
T35	182696	0	0	0
T36	0	3652	0	0
T37	0	4101	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769779518	3650029	0	0
T1	699443	13182	0	0
T2	1648957	14797	0	0
T3	1502644	10542	0	0
T4	750267	13336	0	0
T5	119939	1344	0	0
T6	1070757	9175	0	0
T7	100363	832	0	0
T8	49475	2112	0	0
T9	224496	832	0	0
T10	2695	200	0	0
T11	1308180	3060	0	0
T12	96891	0	0	0
T13	0	3631	0	0
T14	0	9026	0	0
T25	0	13534	0	0
T26	0	8928	0	0
T27	0	7694	0	0
T34	0	1714	0	0
T35	182696	0	0	0
T36	0	3652	0	0
T37	0	4101	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769779518	617048053	0	0
T1	699443	697611	0	0
T2	1648957	1646015	0	0
T3	1502644	1205681	0	0
T4	750267	424821	0	0
T5	119939	68066	0	0
T6	1070757	622112	0	0
T7	100363	80958	0	0
T8	49475	28887	0	0
T9	224496	202333	0	0
T10	2695	2598	0	0
T11	1308180	650513	0	0
T12	96891	93120	0	0
T13	0	132936	0	0
T14	0	678168	0	0
T24	0	104136	0	0
T25	0	74464	0	0
T26	0	14096	0	0
T27	0	22040	0	0
T35	182696	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769779518	617048053	0	0
T1	699443	697611	0	0
T2	1648957	1646015	0	0
T3	1502644	1205681	0	0
T4	750267	424821	0	0
T5	119939	68066	0	0
T6	1070757	622112	0	0
T7	100363	80958	0	0
T8	49475	28887	0	0
T9	224496	202333	0	0
T10	2695	2598	0	0
T11	1308180	650513	0	0
T12	96891	93120	0	0
T13	0	132936	0	0
T14	0	678168	0	0
T24	0	104136	0	0
T25	0	74464	0	0
T26	0	14096	0	0
T27	0	22040	0	0
T35	182696	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769779518	3650029	0	0
T1	699443	13182	0	0
T2	1648957	14797	0	0
T3	1502644	10542	0	0
T4	750267	13336	0	0
T5	119939	1344	0	0
T6	1070757	9175	0	0
T7	100363	832	0	0
T8	49475	2112	0	0
T9	224496	832	0	0
T10	2695	200	0	0
T11	1308180	3060	0	0
T12	96891	0	0	0
T13	0	3631	0	0
T14	0	9026	0	0
T25	0	13534	0	0
T26	0	8928	0	0
T27	0	7694	0	0
T34	0	1714	0	0
T35	182696	0	0	0
T36	0	3652	0	0
T37	0	4101	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769779518	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769779518	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769779518	3650029	0	0
T1	699443	13182	0	0
T2	1648957	14797	0	0
T3	1502644	10542	0	0
T4	750267	13336	0	0
T5	119939	1344	0	0
T6	1070757	9175	0	0
T7	100363	832	0	0
T8	49475	2112	0	0
T9	224496	832	0	0
T10	2695	200	0	0
T11	1308180	3060	0	0
T12	96891	0	0	0
T13	0	3631	0	0
T14	0	9026	0	0
T25	0	13534	0	0
T26	0	8928	0	0
T27	0	7694	0	0
T34	0	1714	0	0
T35	182696	0	0	0
T36	0	3652	0	0
T37	0	4101	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769779518	3650029	0	0
T1	699443	13182	0	0
T2	1648957	14797	0	0
T3	1502644	10542	0	0
T4	750267	13336	0	0
T5	119939	1344	0	0
T6	1070757	9175	0	0
T7	100363	832	0	0
T8	49475	2112	0	0
T9	224496	832	0	0
T10	2695	200	0	0
T11	1308180	3060	0	0
T12	96891	0	0	0
T13	0	3631	0	0
T14	0	9026	0	0
T25	0	13534	0	0
T26	0	8928	0	0
T27	0	7694	0	0
T34	0	1714	0	0
T35	182696	0	0	0
T36	0	3652	0	0
T37	0	4101	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769779518	3650029	0	0
T1	699443	13182	0	0
T2	1648957	14797	0	0
T3	1502644	10542	0	0
T4	750267	13336	0	0
T5	119939	1344	0	0
T6	1070757	9175	0	0
T7	100363	832	0	0
T8	49475	2112	0	0
T9	224496	832	0	0
T10	2695	200	0	0
T11	1308180	3060	0	0
T12	96891	0	0	0
T13	0	3631	0	0
T14	0	9026	0	0
T25	0	13534	0	0
T26	0	8928	0	0
T27	0	7694	0	0
T34	0	1714	0	0
T35	182696	0	0	0
T36	0	3652	0	0
T37	0	4101	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	769779518	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769779518	0	0	974

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769779518	617048053	0	0
T1	699443	697611	0	0
T2	1648957	1646015	0	0
T3	1502644	1205681	0	0
T4	750267	424821	0	0
T5	119939	68066	0	0
T6	1070757	622112	0	0
T7	100363	80958	0	0
T8	49475	28887	0	0
T9	224496	202333	0	0
T10	2695	2598	0	0
T11	1308180	650513	0	0
T12	96891	93120	0	0
T13	0	132936	0	0
T14	0	678168	0	0
T24	0	104136	0	0
T25	0	74464	0	0
T26	0	14096	0	0
T27	0	22040	0	0
T35	182696	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769779518	3650029	0	0
T1	699443	13182	0	0
T2	1648957	14797	0	0
T3	1502644	10542	0	0
T4	750267	13336	0	0
T5	119939	1344	0	0
T6	1070757	9175	0	0
T7	100363	832	0	0
T8	49475	2112	0	0
T9	224496	832	0	0
T10	2695	200	0	0
T11	1308180	3060	0	0
T12	96891	0	0	0
T13	0	3631	0	0
T14	0	9026	0	0
T25	0	13534	0	0
T26	0	8928	0	0
T27	0	7694	0	0
T34	0	1714	0	0
T35	182696	0	0	0
T36	0	3652	0	0
T37	0	4101	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T11
1	0	Covered	T3,T6,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T11
1	0	Unreachable
1	1	Covered	T3,T6,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T6,T11
0	0	1	Unreachable
0	0	0	Covered	T3,T6,T11

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	151282566	29860352	0	0
CheckNGreaterZero_A	974	974	0	0
GntImpliesReady_A	151282566	615997	0	0
GntImpliesValid_A	151282566	615997	0	0
GrantKnown_A	151282566	29860352	0	0
IdxKnown_A	151282566	29860352	0	0
IndexIsCorrect_A	151282566	615997	0	0
LockArbDecision_A	151282566	0	0	0
NoReadyValidNoGrant_A	151282566	0	0	0
ReadyAndValidImplyGrant_A	151282566	615997	0	0
ReqAndReadyImplyGrant_A	151282566	615997	0	0
ReqImpliesValid_A	151282566	615997	0	0
ReqStaysHighUntilGranted0_M	151282566	0	0	0
RoundRobin_A	151282566	0	0	0
ValidKnown_A	151282566	29860352	0	0
gen_data_port_assertion.DataFlow_A	151282566	615997	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151282566	29860352	0	0
T3	295682	10408	0	0
T4	322241	0	0	0
T5	51809	0	0	0
T6	445651	24872	0	0
T7	19178	0	0	0
T8	20530	0	0	0
T9	22107	0	0	0
T11	654090	33720	0	0
T12	96891	93120	0	0
T13	0	132936	0	0
T14	0	678168	0	0
T24	0	104136	0	0
T25	0	74464	0	0
T26	0	14096	0	0
T27	0	22040	0	0
T35	182696	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974	974	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151282566	615997	0	0
T3	295682	344	0	0
T4	322241	0	0	0
T5	51809	0	0	0
T6	445651	994	0	0
T7	19178	0	0	0
T8	20530	0	0	0
T9	22107	0	0	0
T11	654090	1368	0	0
T12	96891	0	0	0
T13	0	3631	0	0
T14	0	9026	0	0
T25	0	2852	0	0
T26	0	423	0	0
T27	0	824	0	0
T35	182696	0	0	0
T36	0	3652	0	0
T37	0	4101	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151282566	615997	0	0
T3	295682	344	0	0
T4	322241	0	0	0
T5	51809	0	0	0
T6	445651	994	0	0
T7	19178	0	0	0
T8	20530	0	0	0
T9	22107	0	0	0
T11	654090	1368	0	0
T12	96891	0	0	0
T13	0	3631	0	0
T14	0	9026	0	0
T25	0	2852	0	0
T26	0	423	0	0
T27	0	824	0	0
T35	182696	0	0	0
T36	0	3652	0	0
T37	0	4101	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151282566	29860352	0	0
T3	295682	10408	0	0
T4	322241	0	0	0
T5	51809	0	0	0
T6	445651	24872	0	0
T7	19178	0	0	0
T8	20530	0	0	0
T9	22107	0	0	0
T11	654090	33720	0	0
T12	96891	93120	0	0
T13	0	132936	0	0
T14	0	678168	0	0
T24	0	104136	0	0
T25	0	74464	0	0
T26	0	14096	0	0
T27	0	22040	0	0
T35	182696	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151282566	29860352	0	0
T3	295682	10408	0	0
T4	322241	0	0	0
T5	51809	0	0	0
T6	445651	24872	0	0
T7	19178	0	0	0
T8	20530	0	0	0
T9	22107	0	0	0
T11	654090	33720	0	0
T12	96891	93120	0	0
T13	0	132936	0	0
T14	0	678168	0	0
T24	0	104136	0	0
T25	0	74464	0	0
T26	0	14096	0	0
T27	0	22040	0	0
T35	182696	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151282566	615997	0	0
T3	295682	344	0	0
T4	322241	0	0	0
T5	51809	0	0	0
T6	445651	994	0	0
T7	19178	0	0	0
T8	20530	0	0	0
T9	22107	0	0	0
T11	654090	1368	0	0
T12	96891	0	0	0
T13	0	3631	0	0
T14	0	9026	0	0
T25	0	2852	0	0
T26	0	423	0	0
T27	0	824	0	0
T35	182696	0	0	0
T36	0	3652	0	0
T37	0	4101	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151282566	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151282566	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151282566	615997	0	0
T3	295682	344	0	0
T4	322241	0	0	0
T5	51809	0	0	0
T6	445651	994	0	0
T7	19178	0	0	0
T8	20530	0	0	0
T9	22107	0	0	0
T11	654090	1368	0	0
T12	96891	0	0	0
T13	0	3631	0	0
T14	0	9026	0	0
T25	0	2852	0	0
T26	0	423	0	0
T27	0	824	0	0
T35	182696	0	0	0
T36	0	3652	0	0
T37	0	4101	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151282566	615997	0	0
T3	295682	344	0	0
T4	322241	0	0	0
T5	51809	0	0	0
T6	445651	994	0	0
T7	19178	0	0	0
T8	20530	0	0	0
T9	22107	0	0	0
T11	654090	1368	0	0
T12	96891	0	0	0
T13	0	3631	0	0
T14	0	9026	0	0
T25	0	2852	0	0
T26	0	423	0	0
T27	0	824	0	0
T35	182696	0	0	0
T36	0	3652	0	0
T37	0	4101	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151282566	615997	0	0
T3	295682	344	0	0
T4	322241	0	0	0
T5	51809	0	0	0
T6	445651	994	0	0
T7	19178	0	0	0
T8	20530	0	0	0
T9	22107	0	0	0
T11	654090	1368	0	0
T12	96891	0	0	0
T13	0	3631	0	0
T14	0	9026	0	0
T25	0	2852	0	0
T26	0	423	0	0
T27	0	824	0	0
T35	182696	0	0	0
T36	0	3652	0	0
T37	0	4101	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	151282566	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151282566	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151282566	29860352	0	0
T3	295682	10408	0	0
T4	322241	0	0	0
T5	51809	0	0	0
T6	445651	24872	0	0
T7	19178	0	0	0
T8	20530	0	0	0
T9	22107	0	0	0
T11	654090	33720	0	0
T12	96891	93120	0	0
T13	0	132936	0	0
T14	0	678168	0	0
T24	0	104136	0	0
T25	0	74464	0	0
T26	0	14096	0	0
T27	0	22040	0	0
T35	182696	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151282566	615997	0	0
T3	295682	344	0	0
T4	322241	0	0	0
T5	51809	0	0	0
T6	445651	994	0	0
T7	19178	0	0	0
T8	20530	0	0	0
T9	22107	0	0	0
T11	654090	1368	0	0
T12	96891	0	0	0
T13	0	3631	0	0
T14	0	9026	0	0
T25	0	2852	0	0
T26	0	423	0	0
T27	0	824	0	0
T35	182696	0	0	0
T36	0	3652	0	0
T37	0	4101	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	151282566	120061253	0	0
CheckNGreaterZero_A	974	974	0	0
GntImpliesReady_A	151282566	760168	0	0
GntImpliesValid_A	151282566	760168	0	0
GrantKnown_A	151282566	120061253	0	0
IdxKnown_A	151282566	120061253	0	0
IndexIsCorrect_A	151282566	760168	0	0
LockArbDecision_A	151282566	0	0	0
NoReadyValidNoGrant_A	151282566	0	0	0
ReadyAndValidImplyGrant_A	151282566	760168	0	0
ReqAndReadyImplyGrant_A	151282566	760168	0	0
ReqImpliesValid_A	151282566	760168	0	0
ReqStaysHighUntilGranted0_M	151282566	0	0	0
RoundRobin_A	151282566	0	0	0
ValidKnown_A	151282566	120061253	0	0
gen_data_port_assertion.DataFlow_A	151282566	760168	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151282566	120061253	0	0
T1	462587	460760	0	0
T2	793277	790401	0	0
T3	295682	284209	0	0
T4	322241	319046	0	0
T5	51809	51809	0	0
T6	445651	417794	0	0
T7	19178	19010	0	0
T8	20530	20530	0	0
T9	22107	22107	0	0
T11	654090	616793	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974	974	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151282566	760168	0	0
T1	462587	4572	0	0
T2	793277	5375	0	0
T3	295682	7250	0	0
T4	322241	4213	0	0
T5	51809	0	0	0
T6	445651	1856	0	0
T7	19178	0	0	0
T8	20530	0	0	0
T9	22107	0	0	0
T11	654090	1692	0	0
T25	0	10682	0	0
T26	0	8505	0	0
T27	0	6870	0	0
T34	0	1714	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151282566	760168	0	0
T1	462587	4572	0	0
T2	793277	5375	0	0
T3	295682	7250	0	0
T4	322241	4213	0	0
T5	51809	0	0	0
T6	445651	1856	0	0
T7	19178	0	0	0
T8	20530	0	0	0
T9	22107	0	0	0
T11	654090	1692	0	0
T25	0	10682	0	0
T26	0	8505	0	0
T27	0	6870	0	0
T34	0	1714	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151282566	120061253	0	0
T1	462587	460760	0	0
T2	793277	790401	0	0
T3	295682	284209	0	0
T4	322241	319046	0	0
T5	51809	51809	0	0
T6	445651	417794	0	0
T7	19178	19010	0	0
T8	20530	20530	0	0
T9	22107	22107	0	0
T11	654090	616793	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151282566	120061253	0	0
T1	462587	460760	0	0
T2	793277	790401	0	0
T3	295682	284209	0	0
T4	322241	319046	0	0
T5	51809	51809	0	0
T6	445651	417794	0	0
T7	19178	19010	0	0
T8	20530	20530	0	0
T9	22107	22107	0	0
T11	654090	616793	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151282566	760168	0	0
T1	462587	4572	0	0
T2	793277	5375	0	0
T3	295682	7250	0	0
T4	322241	4213	0	0
T5	51809	0	0	0
T6	445651	1856	0	0
T7	19178	0	0	0
T8	20530	0	0	0
T9	22107	0	0	0
T11	654090	1692	0	0
T25	0	10682	0	0
T26	0	8505	0	0
T27	0	6870	0	0
T34	0	1714	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151282566	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151282566	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151282566	760168	0	0
T1	462587	4572	0	0
T2	793277	5375	0	0
T3	295682	7250	0	0
T4	322241	4213	0	0
T5	51809	0	0	0
T6	445651	1856	0	0
T7	19178	0	0	0
T8	20530	0	0	0
T9	22107	0	0	0
T11	654090	1692	0	0
T25	0	10682	0	0
T26	0	8505	0	0
T27	0	6870	0	0
T34	0	1714	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151282566	760168	0	0
T1	462587	4572	0	0
T2	793277	5375	0	0
T3	295682	7250	0	0
T4	322241	4213	0	0
T5	51809	0	0	0
T6	445651	1856	0	0
T7	19178	0	0	0
T8	20530	0	0	0
T9	22107	0	0	0
T11	654090	1692	0	0
T25	0	10682	0	0
T26	0	8505	0	0
T27	0	6870	0	0
T34	0	1714	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151282566	760168	0	0
T1	462587	4572	0	0
T2	793277	5375	0	0
T3	295682	7250	0	0
T4	322241	4213	0	0
T5	51809	0	0	0
T6	445651	1856	0	0
T7	19178	0	0	0
T8	20530	0	0	0
T9	22107	0	0	0
T11	654090	1692	0	0
T25	0	10682	0	0
T26	0	8505	0	0
T27	0	6870	0	0
T34	0	1714	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	151282566	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151282566	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151282566	120061253	0	0
T1	462587	460760	0	0
T2	793277	790401	0	0
T3	295682	284209	0	0
T4	322241	319046	0	0
T5	51809	51809	0	0
T6	445651	417794	0	0
T7	19178	19010	0	0
T8	20530	20530	0	0
T9	22107	22107	0	0
T11	654090	616793	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151282566	760168	0	0
T1	462587	4572	0	0
T2	793277	5375	0	0
T3	295682	7250	0	0
T4	322241	4213	0	0
T5	51809	0	0	0
T6	445651	1856	0	0
T7	19178	0	0	0
T8	20530	0	0	0
T9	22107	0	0	0
T11	654090	1692	0	0
T25	0	10682	0	0
T26	0	8505	0	0
T27	0	6870	0	0
T34	0	1714	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	467214386	467126448	0	0
CheckNGreaterZero_A	974	974	0	0
GntImpliesReady_A	467214386	2273864	0	0
GntImpliesValid_A	467214386	2273864	0	0
GrantKnown_A	467214386	467126448	0	0
IdxKnown_A	467214386	467126448	0	0
IndexIsCorrect_A	467214386	2273864	0	0
LockArbDecision_A	467214386	0	0	0
NoReadyValidNoGrant_A	467214386	0	0	0
ReadyAndValidImplyGrant_A	467214386	2273864	0	0
ReqAndReadyImplyGrant_A	467214386	2273864	0	0
ReqImpliesValid_A	467214386	2273864	0	0
ReqStaysHighUntilGranted0_M	467214386	0	0	0
RoundRobin_A	467214386	0	0	974
ValidKnown_A	467214386	467126448	0	0
gen_data_port_assertion.DataFlow_A	467214386	2273864	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467214386	467126448	0	0
T1	236856	236851	0	0
T2	855680	855614	0	0
T3	911280	911064	0	0
T4	105785	105775	0	0
T5	16321	16257	0	0
T6	179455	179446	0	0
T7	62007	61948	0	0
T8	8415	8357	0	0
T9	180282	180226	0	0
T10	2695	2598	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974	974	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467214386	2273864	0	0
T1	236856	8610	0	0
T2	855680	9422	0	0
T3	911280	2948	0	0
T4	105785	9123	0	0
T5	16321	1344	0	0
T6	179455	6325	0	0
T7	62007	832	0	0
T8	8415	2112	0	0
T9	180282	832	0	0
T10	2695	200	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467214386	2273864	0	0
T1	236856	8610	0	0
T2	855680	9422	0	0
T3	911280	2948	0	0
T4	105785	9123	0	0
T5	16321	1344	0	0
T6	179455	6325	0	0
T7	62007	832	0	0
T8	8415	2112	0	0
T9	180282	832	0	0
T10	2695	200	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467214386	467126448	0	0
T1	236856	236851	0	0
T2	855680	855614	0	0
T3	911280	911064	0	0
T4	105785	105775	0	0
T5	16321	16257	0	0
T6	179455	179446	0	0
T7	62007	61948	0	0
T8	8415	8357	0	0
T9	180282	180226	0	0
T10	2695	2598	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467214386	467126448	0	0
T1	236856	236851	0	0
T2	855680	855614	0	0
T3	911280	911064	0	0
T4	105785	105775	0	0
T5	16321	16257	0	0
T6	179455	179446	0	0
T7	62007	61948	0	0
T8	8415	8357	0	0
T9	180282	180226	0	0
T10	2695	2598	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467214386	2273864	0	0
T1	236856	8610	0	0
T2	855680	9422	0	0
T3	911280	2948	0	0
T4	105785	9123	0	0
T5	16321	1344	0	0
T6	179455	6325	0	0
T7	62007	832	0	0
T8	8415	2112	0	0
T9	180282	832	0	0
T10	2695	200	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467214386	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467214386	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467214386	2273864	0	0
T1	236856	8610	0	0
T2	855680	9422	0	0
T3	911280	2948	0	0
T4	105785	9123	0	0
T5	16321	1344	0	0
T6	179455	6325	0	0
T7	62007	832	0	0
T8	8415	2112	0	0
T9	180282	832	0	0
T10	2695	200	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467214386	2273864	0	0
T1	236856	8610	0	0
T2	855680	9422	0	0
T3	911280	2948	0	0
T4	105785	9123	0	0
T5	16321	1344	0	0
T6	179455	6325	0	0
T7	62007	832	0	0
T8	8415	2112	0	0
T9	180282	832	0	0
T10	2695	200	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467214386	2273864	0	0
T1	236856	8610	0	0
T2	855680	9422	0	0
T3	911280	2948	0	0
T4	105785	9123	0	0
T5	16321	1344	0	0
T6	179455	6325	0	0
T7	62007	832	0	0
T8	8415	2112	0	0
T9	180282	832	0	0
T10	2695	200	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	467214386	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467214386	0	0	974

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467214386	467126448	0	0
T1	236856	236851	0	0
T2	855680	855614	0	0
T3	911280	911064	0	0
T4	105785	105775	0	0
T5	16321	16257	0	0
T6	179455	179446	0	0
T7	62007	61948	0	0
T8	8415	8357	0	0
T9	180282	180226	0	0
T10	2695	2598	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467214386	2273864	0	0
T1	236856	8610	0	0
T2	855680	9422	0	0
T3	911280	2948	0	0
T4	105785	9123	0	0
T5	16321	1344	0	0
T6	179455	6325	0	0
T7	62007	832	0	0
T8	8415	2112	0	0
T9	180282	832	0	0
T10	2695	200	0	0