Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3602998	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4206210

1

T1

2

T2

1300

T3

888

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4319280	1			T1	1		T2	842		T3	5
values[0x0]	1744053	1			T1	5		T2	425		T3	458
values[0x1]	1745875	1			T1	5		T2	459		T3	432

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2554623	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5254585

1

T1

2

T2

1394

T3

893

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28935	1			T2	6		T3	3		T7	83
valid_sources[0x01]	29263	1			T2	7		T5	2		T7	230
valid_sources[0x02]	33851	1			T2	6		T3	13		T5	3
valid_sources[0x03]	34580	1			T2	9		T3	1		T4	1
valid_sources[0x04]	28039	1			T2	4		T3	3		T4	1
valid_sources[0x05]	30021	1			T2	5		T5	162		T7	241
valid_sources[0x06]	29966	1			T2	3		T3	4		T4	1
valid_sources[0x07]	29622	1			T2	5		T3	2		T4	1
valid_sources[0x08]	28557	1			T1	1		T2	3		T3	3
valid_sources[0x09]	30479	1			T2	7		T4	2		T5	26
valid_sources[0x0a]	31515	1			T2	5		T3	3		T5	239
valid_sources[0x0b]	32351	1			T2	11		T3	1		T4	1
valid_sources[0x0c]	33970	1			T1	1		T2	3		T3	10
valid_sources[0x0d]	26755	1			T2	2		T3	1		T5	1
valid_sources[0x0e]	28788	1			T2	4		T4	2		T7	73
valid_sources[0x0f]	31955	1			T2	7		T4	1		T5	16
valid_sources[0x10]	28321	1			T2	11		T4	2		T5	34
valid_sources[0x11]	30317	1			T2	6		T3	5		T5	2
valid_sources[0x12]	27893	1			T2	6		T4	1		T7	152
valid_sources[0x13]	30466	1			T1	1		T2	9		T3	3
valid_sources[0x14]	29526	1			T2	5		T3	6		T5	1
valid_sources[0x15]	31895	1			T2	5		T3	4		T7	324
valid_sources[0x16]	30000	1			T2	8		T3	18		T4	1
valid_sources[0x17]	30779	1			T2	13		T3	2		T7	102
valid_sources[0x18]	33896	1			T2	10		T3	1		T4	2
valid_sources[0x19]	29330	1			T2	5		T4	1		T5	62
valid_sources[0x1a]	27473	1			T2	9		T3	1		T7	203
valid_sources[0x1b]	27858	1			T2	10		T7	145		T8	125
valid_sources[0x1c]	29691	1			T2	4		T3	4		T6	452
valid_sources[0x1d]	30844	1			T2	7		T3	1		T4	1
valid_sources[0x1e]	30354	1			T2	8		T3	1		T4	2
valid_sources[0x1f]	27585	1			T2	4		T3	7		T5	28
valid_sources[0x20]	29565	1			T2	11		T3	9		T4	1
valid_sources[0x21]	33038	1			T2	4		T5	227		T7	119
valid_sources[0x22]	26364	1			T2	2		T3	4		T4	1
valid_sources[0x23]	34281	1			T2	7		T5	23		T7	286
valid_sources[0x24]	28878	1			T2	6		T3	2		T7	66
valid_sources[0x25]	34458	1			T2	7		T3	2		T4	1
valid_sources[0x26]	29841	1			T2	9		T3	5		T7	144
valid_sources[0x27]	26335	1			T2	6		T3	18		T4	1
valid_sources[0x28]	29595	1			T2	7		T3	2		T5	51
valid_sources[0x29]	38104	1			T2	7		T3	6		T5	1
valid_sources[0x2a]	28636	1			T2	5		T4	1		T7	125
valid_sources[0x2b]	30683	1			T2	8		T4	2		T5	1
valid_sources[0x2c]	37997	1			T2	11		T3	3		T4	3
valid_sources[0x2d]	27868	1			T2	8		T3	4		T4	1
valid_sources[0x2e]	31337	1			T2	5		T3	8		T4	1
valid_sources[0x2f]	36988	1			T2	5		T7	189		T8	126
valid_sources[0x30]	31794	1			T2	5		T3	3		T5	9
valid_sources[0x31]	27820	1			T2	7		T4	2		T5	2
valid_sources[0x32]	28170	1			T2	7		T3	13		T5	134
valid_sources[0x33]	26743	1			T2	9		T3	1		T5	1
valid_sources[0x34]	28239	1			T2	4		T3	5		T7	195
valid_sources[0x35]	29328	1			T2	7		T3	10		T4	2
valid_sources[0x36]	25823	1			T2	8		T3	2		T4	1
valid_sources[0x37]	27854	1			T2	9		T3	4		T5	220
valid_sources[0x38]	34647	1			T2	6		T3	1		T5	115
valid_sources[0x39]	26821	1			T2	4		T3	6		T4	1
valid_sources[0x3a]	34585	1			T2	7		T4	1		T7	216
valid_sources[0x3b]	34022	1			T2	7		T5	9		T7	147
valid_sources[0x3c]	30489	1			T2	5		T3	9		T7	65
valid_sources[0x3d]	32490	1			T2	6		T3	3		T4	2
valid_sources[0x3e]	37172	1			T2	9		T4	3		T5	31
valid_sources[0x3f]	28081	1			T2	8		T4	4		T5	83
valid_sources[0x40]	30865	1			T2	7		T4	1		T5	49
valid_sources[0x41]	29972	1			T2	6		T3	2		T4	3
valid_sources[0x42]	27650	1			T2	8		T3	10		T4	1
valid_sources[0x43]	30702	1			T2	7		T3	5		T4	2
valid_sources[0x44]	27494	1			T1	1		T2	7		T3	6
valid_sources[0x45]	30913	1			T2	10		T4	1		T5	60
valid_sources[0x46]	26743	1			T2	4		T3	2		T7	75
valid_sources[0x47]	29319	1			T2	6		T4	4		T7	144
valid_sources[0x48]	34717	1			T2	6		T3	11		T5	294
valid_sources[0x49]	62650	1			T2	5		T3	1		T4	3
valid_sources[0x4a]	30592	1			T2	6		T3	6		T4	1
valid_sources[0x4b]	28556	1			T2	9		T3	9		T4	1
valid_sources[0x4c]	33015	1			T2	6		T3	2		T5	258
valid_sources[0x4d]	30932	1			T1	1		T2	10		T5	131
valid_sources[0x4e]	64549	1			T2	7		T3	8		T5	1
valid_sources[0x4f]	28311	1			T2	5		T5	28		T6	712
valid_sources[0x50]	26819	1			T2	5		T3	1		T4	1
valid_sources[0x51]	29007	1			T2	6		T3	5		T5	7
valid_sources[0x52]	33226	1			T2	7		T3	2		T5	2
valid_sources[0x53]	32045	1			T2	5		T3	3		T4	1
valid_sources[0x54]	26981	1			T2	10		T3	5		T7	184
valid_sources[0x55]	28275	1			T2	9		T3	2		T4	1
valid_sources[0x56]	30551	1			T1	2		T2	8		T3	3
valid_sources[0x57]	30042	1			T2	5		T3	1		T4	2
valid_sources[0x58]	29375	1			T2	6		T3	14		T4	2
valid_sources[0x59]	28568	1			T2	7		T4	1		T5	12
valid_sources[0x5a]	28463	1			T2	5		T7	124		T8	88
valid_sources[0x5b]	29731	1			T2	6		T3	3		T4	1
valid_sources[0x5c]	32002	1			T2	4		T3	1		T4	2
valid_sources[0x5d]	29071	1			T2	9		T3	11		T7	166
valid_sources[0x5e]	29952	1			T2	6		T3	7		T5	1
valid_sources[0x5f]	27708	1			T2	7		T7	193		T8	106
valid_sources[0x60]	31378	1			T2	6		T4	3		T5	391
valid_sources[0x61]	29672	1			T2	6		T3	6		T5	1
valid_sources[0x62]	28902	1			T2	7		T3	15		T4	1
valid_sources[0x63]	31358	1			T2	4		T4	1		T5	151
valid_sources[0x64]	28898	1			T2	5		T5	24		T7	196
valid_sources[0x65]	28453	1			T2	10		T3	4		T4	1
valid_sources[0x66]	27246	1			T2	4		T4	1		T7	117
valid_sources[0x67]	29324	1			T2	8		T3	2		T4	1
valid_sources[0x68]	30841	1			T2	8		T5	17		T7	142
valid_sources[0x69]	27803	1			T2	9		T3	3		T4	1
valid_sources[0x6a]	30564	1			T2	2		T4	2		T5	1
valid_sources[0x6b]	29053	1			T2	8		T3	1		T5	4
valid_sources[0x6c]	30053	1			T2	7		T3	12		T4	1
valid_sources[0x6d]	28046	1			T2	8		T3	1		T4	2
valid_sources[0x6e]	31289	1			T2	6		T3	13		T4	2
valid_sources[0x6f]	30912	1			T2	4		T4	1		T5	139
valid_sources[0x70]	30275	1			T2	5		T3	10		T4	1
valid_sources[0x71]	34401	1			T2	6		T4	1		T5	59
valid_sources[0x72]	32844	1			T2	4		T3	4		T7	260
valid_sources[0x73]	28887	1			T2	10		T3	8		T4	1
valid_sources[0x74]	29448	1			T2	6		T3	6		T5	24
valid_sources[0x75]	33377	1			T2	7		T4	2		T5	29
valid_sources[0x76]	27189	1			T2	6		T3	2		T7	60
valid_sources[0x77]	28891	1			T2	7		T3	1		T7	43
valid_sources[0x78]	29626	1			T2	8		T3	4		T5	3
valid_sources[0x79]	36927	1			T2	8		T3	2		T7	83
valid_sources[0x7a]	32580	1			T2	8		T3	6		T4	2
valid_sources[0x7b]	29427	1			T2	9		T3	15		T7	157
valid_sources[0x7c]	26858	1			T2	13		T3	2		T7	47
valid_sources[0x7d]	30080	1			T2	8		T3	7		T7	93
valid_sources[0x7e]	28744	1			T2	10		T3	13		T4	2
valid_sources[0x7f]	26678	1			T2	3		T3	1		T7	207
valid_sources[0x80]	36115	1			T2	8		T5	206		T7	84

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1043650

1

T1

1

T2

422

T3

1

values[0x0]

all_enables

biggest_size

1592672

1

T1

1

T2

425

T3

458

values[0x1]

all_enables

biggest_size

1569888

1

T2

453

T3

429

T4

4