Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3625190

1

T1

9

T2

426

T3

7

full_word

4205500

1

T1

2

T2

1300

T3

888

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7830280	1			T1	11		T2	1726		T3	895
auto[TlIntgErrCmd]	152	1			T92	5		T94	3		T93	9
auto[TlIntgErrData]	132	1			T92	2		T94	2		T93	11
auto[TlIntgErrBoth]	126	1			T92	3		T94	5		T93	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4322386

1

T1

1

T2

842

T3

5

auto[1]

3508304

1

T1

10

T2

884

T3

890

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3278333	1			T2	420		T3	4		T4	107
auto[TlIntgErrNone]	partial	auto[1]	346482	1			T1	9		T2	6		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	1043866	1			T1	1		T2	422		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	3161599	1			T1	1		T2	878		T3	887
auto[TlIntgErrCmd]	partial	auto[0]	61	1			T92	1		T94	1		T93	5
auto[TlIntgErrCmd]	partial	auto[1]	76	1			T92	4		T94	2		T93	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T249	1		T250	1		T251	1
auto[TlIntgErrCmd]	full_word	auto[1]	12	1			T93	1		T247	1		T252	1
auto[TlIntgErrData]	partial	auto[0]	65	1			T94	1		T93	5		T243	3
auto[TlIntgErrData]	partial	auto[1]	57	1			T92	1		T94	1		T93	6
auto[TlIntgErrData]	full_word	auto[0]	4	1			T249	1		T251	1		T248	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T92	1		T243	1		T249	1
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T94	3		T93	1		T243	4
auto[TlIntgErrBoth]	partial	auto[1]	67	1			T92	1		T94	2		T93	7
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T92	2		T93	1		T247	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T93	1		T253	1		T247	1