Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T5,T7,T12
1	0	Covered	T5,T7,T12
1	1	Covered	T7,T12,T13

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T12
1	0	Covered	T7,T12,T13
1	1	Covered	T5,T7,T12

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1377737073	2723	0	0
SrcPulseCheck_M	430224285	2723	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1377737073	2723	0	0
T5	916060	1	0	0
T6	648946	0	0	0
T7	481287	8	0	0
T8	419502	0	0	0
T9	809	0	0	0
T10	195664	0	0	0
T11	4795	0	0	0
T12	464988	18	0	0
T13	344868	7	0	0
T14	130056	0	0	0
T15	18130	0	0	0
T24	1866	0	0	0
T25	159006	0	0	0
T26	232744	18	0	0
T27	17486	0	0	0
T29	0	23	0	0
T30	0	11	0	0
T34	2256	0	0	0
T37	0	11	0	0
T38	0	11	0	0
T39	284804	6	0	0
T40	0	3	0	0
T46	0	2	0	0
T47	0	4	0	0
T50	0	7	0	0
T81	0	9	0	0
T107	9128	0	0	0
T139	0	15	0	0
T140	0	7	0	0
T141	0	7	0	0
T142	0	7	0	0
T143	0	7	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430224285	2723	0	0
T5	112799	1	0	0
T6	92160	0	0	0
T7	946944	8	0	0
T8	52112	0	0	0
T10	25455	0	0	0
T11	2325	0	0	0
T12	714554	18	0	0
T13	51528	7	0	0
T14	12336	0	0	0
T15	5529	0	0	0
T25	194558	0	0	0
T26	1133242	18	0	0
T27	2446	0	0	0
T29	0	23	0	0
T30	0	11	0	0
T37	0	11	0	0
T38	0	11	0	0
T39	69374	6	0	0
T40	0	3	0	0
T46	0	2	0	0
T47	0	4	0	0
T50	0	7	0	0
T79	224	0	0	0
T81	0	9	0	0
T107	160	0	0	0
T139	0	15	0	0
T140	0	7	0	0
T141	0	7	0	0
T142	0	7	0	0
T143	0	7	0	0
T144	54798	0	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T13,T39,T40
1	0	Covered	T13,T39,T40
1	1	Covered	T13,T39,T40

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T39,T40
1	0	Covered	T13,T39,T40
1	1	Covered	T13,T39,T40

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	459245691	169	0	0
SrcPulseCheck_M	143408095	169	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459245691	169	0	0
T13	114956	2	0	0
T14	43352	0	0	0
T15	9065	0	0	0
T24	933	0	0	0
T25	79503	0	0	0
T26	116372	0	0	0
T27	8743	0	0	0
T34	1128	0	0	0
T39	142402	3	0	0
T40	0	2	0	0
T50	0	2	0	0
T81	0	5	0	0
T107	4564	0	0	0
T139	0	8	0	0
T140	0	2	0	0
T141	0	2	0	0
T142	0	2	0	0
T143	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	169	0	0
T13	17176	2	0	0
T14	4112	0	0	0
T15	1843	0	0	0
T25	97279	0	0	0
T26	566621	0	0	0
T27	1223	0	0	0
T39	34687	3	0	0
T40	0	2	0	0
T50	0	2	0	0
T79	112	0	0	0
T81	0	5	0	0
T107	80	0	0	0
T139	0	8	0	0
T140	0	2	0	0
T141	0	2	0	0
T142	0	2	0	0
T143	0	2	0	0
T144	27399	0	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T13,T39,T40
1	0	Covered	T13,T39,T40
1	1	Covered	T13,T39,T50

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T39,T40
1	0	Covered	T13,T39,T50
1	1	Covered	T13,T39,T40

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	459245691	327	0	0
SrcPulseCheck_M	143408095	327	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459245691	327	0	0
T13	114956	5	0	0
T14	43352	0	0	0
T15	9065	0	0	0
T24	933	0	0	0
T25	79503	0	0	0
T26	116372	0	0	0
T27	8743	0	0	0
T34	1128	0	0	0
T39	142402	3	0	0
T40	0	1	0	0
T50	0	5	0	0
T81	0	4	0	0
T107	4564	0	0	0
T139	0	7	0	0
T140	0	5	0	0
T141	0	5	0	0
T142	0	5	0	0
T143	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	327	0	0
T13	17176	5	0	0
T14	4112	0	0	0
T15	1843	0	0	0
T25	97279	0	0	0
T26	566621	0	0	0
T27	1223	0	0	0
T39	34687	3	0	0
T40	0	1	0	0
T50	0	5	0	0
T79	112	0	0	0
T81	0	4	0	0
T107	80	0	0	0
T139	0	7	0	0
T140	0	5	0	0
T141	0	5	0	0
T142	0	5	0	0
T143	0	5	0	0
T144	27399	0	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T5,T7,T12
1	0	Covered	T5,T7,T12
1	1	Covered	T7,T12,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T12
1	0	Covered	T7,T12,T26
1	1	Covered	T5,T7,T12

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	459245691	2227	0	0
SrcPulseCheck_M	143408095	2227	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459245691	2227	0	0
T5	916060	1	0	0
T6	648946	0	0	0
T7	481287	8	0	0
T8	419502	0	0	0
T9	809	0	0	0
T10	195664	0	0	0
T11	4795	0	0	0
T12	464988	18	0	0
T13	114956	0	0	0
T14	43352	0	0	0
T26	0	18	0	0
T29	0	23	0	0
T30	0	11	0	0
T37	0	11	0	0
T38	0	11	0	0
T46	0	2	0	0
T47	0	4	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	2227	0	0
T5	112799	1	0	0
T6	92160	0	0	0
T7	946944	8	0	0
T8	52112	0	0	0
T10	25455	0	0	0
T11	2325	0	0	0
T12	714554	18	0	0
T13	17176	0	0	0
T14	4112	0	0	0
T15	1843	0	0	0
T26	0	18	0	0
T29	0	23	0	0
T30	0	11	0	0
T37	0	11	0	0
T38	0	11	0	0
T46	0	2	0	0
T47	0	4	0	0