Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	461676998	2844405	0	0
DepthKnown_A	461676998	461542423	0	0
RvalidKnown_A	461676998	461542423	0	0
WreadyKnown_A	461676998	461542423	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461676998	2844405	0	0
T2	21559	1663	0	0
T3	39416	832	0	0
T4	4093	0	0	0
T5	916060	1663	0	0
T6	648946	1663	0	0
T7	481287	15001	0	0
T8	419502	832	0	0
T9	809	0	0	0
T10	195664	0	0	0
T11	4795	0	0	0
T12	0	14970	0	0
T13	0	832	0	0
T14	0	832	0	0
T34	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461676998	461542423	0	0
T1	844	746	0	0
T2	21559	21499	0	0
T3	39416	39366	0	0
T4	4093	3833	0	0
T5	916060	916009	0	0
T6	648946	648884	0	0
T7	481287	481280	0	0
T8	419502	419433	0	0
T9	809	738	0	0
T10	195664	195591	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461676998	461542423	0	0
T1	844	746	0	0
T2	21559	21499	0	0
T3	39416	39366	0	0
T4	4093	3833	0	0
T5	916060	916009	0	0
T6	648946	648884	0	0
T7	481287	481280	0	0
T8	419502	419433	0	0
T9	809	738	0	0
T10	195664	195591	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461676998	461542423	0	0
T1	844	746	0	0
T2	21559	21499	0	0
T3	39416	39366	0	0
T4	4093	3833	0	0
T5	916060	916009	0	0
T6	648946	648884	0	0
T7	481287	481280	0	0
T8	419502	419433	0	0
T9	809	738	0	0
T10	195664	195591	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	461676998	2984390	0	0
DepthKnown_A	461676998	461542423	0	0
RvalidKnown_A	461676998	461542423	0	0
WreadyKnown_A	461676998	461542423	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461676998	2984390	0	0
T2	21559	832	0	0
T3	39416	832	0	0
T4	4093	0	0	0
T5	916060	832	0	0
T6	648946	832	0	0
T7	481287	34359	0	0
T8	419502	832	0	0
T9	809	0	0	0
T10	195664	0	0	0
T11	4795	0	0	0
T12	0	9984	0	0
T13	0	3694	0	0
T14	0	3724	0	0
T34	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461676998	461542423	0	0
T1	844	746	0	0
T2	21559	21499	0	0
T3	39416	39366	0	0
T4	4093	3833	0	0
T5	916060	916009	0	0
T6	648946	648884	0	0
T7	481287	481280	0	0
T8	419502	419433	0	0
T9	809	738	0	0
T10	195664	195591	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461676998	461542423	0	0
T1	844	746	0	0
T2	21559	21499	0	0
T3	39416	39366	0	0
T4	4093	3833	0	0
T5	916060	916009	0	0
T6	648946	648884	0	0
T7	481287	481280	0	0
T8	419502	419433	0	0
T9	809	738	0	0
T10	195664	195591	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461676998	461542423	0	0
T1	844	746	0	0
T2	21559	21499	0	0
T3	39416	39366	0	0
T4	4093	3833	0	0
T5	916060	916009	0	0
T6	648946	648884	0	0
T7	481287	481280	0	0
T8	419502	419433	0	0
T9	809	738	0	0
T10	195664	195591	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	461676998	186075	0	0
DepthKnown_A	461676998	461542423	0	0
RvalidKnown_A	461676998	461542423	0	0
WreadyKnown_A	461676998	461542423	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461676998	186075	0	0
T5	916060	632	0	0
T6	648946	0	0	0
T7	481287	297	0	0
T8	419502	0	0	0
T9	809	0	0	0
T10	195664	0	0	0
T11	4795	28	0	0
T12	464988	290	0	0
T13	114956	0	0	0
T14	43352	0	0	0
T26	0	1161	0	0
T28	0	41	0	0
T29	0	2488	0	0
T34	0	100	0	0
T37	0	416	0	0
T38	0	270	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461676998	461542423	0	0
T1	844	746	0	0
T2	21559	21499	0	0
T3	39416	39366	0	0
T4	4093	3833	0	0
T5	916060	916009	0	0
T6	648946	648884	0	0
T7	481287	481280	0	0
T8	419502	419433	0	0
T9	809	738	0	0
T10	195664	195591	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461676998	461542423	0	0
T1	844	746	0	0
T2	21559	21499	0	0
T3	39416	39366	0	0
T4	4093	3833	0	0
T5	916060	916009	0	0
T6	648946	648884	0	0
T7	481287	481280	0	0
T8	419502	419433	0	0
T9	809	738	0	0
T10	195664	195591	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461676998	461542423	0	0
T1	844	746	0	0
T2	21559	21499	0	0
T3	39416	39366	0	0
T4	4093	3833	0	0
T5	916060	916009	0	0
T6	648946	648884	0	0
T7	481287	481280	0	0
T8	419502	419433	0	0
T9	809	738	0	0
T10	195664	195591	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	461676998	397622	0	0
DepthKnown_A	461676998	461542423	0	0
RvalidKnown_A	461676998	461542423	0	0
WreadyKnown_A	461676998	461542423	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461676998	397622	0	0
T5	916060	632	0	0
T6	648946	0	0	0
T7	481287	1344	0	0
T8	419502	0	0	0
T9	809	0	0	0
T10	195664	0	0	0
T11	4795	101	0	0
T12	464988	290	0	0
T13	114956	0	0	0
T14	43352	0	0	0
T26	0	3866	0	0
T28	0	41	0	0
T29	0	6930	0	0
T34	0	100	0	0
T37	0	1891	0	0
T38	0	552	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461676998	461542423	0	0
T1	844	746	0	0
T2	21559	21499	0	0
T3	39416	39366	0	0
T4	4093	3833	0	0
T5	916060	916009	0	0
T6	648946	648884	0	0
T7	481287	481280	0	0
T8	419502	419433	0	0
T9	809	738	0	0
T10	195664	195591	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461676998	461542423	0	0
T1	844	746	0	0
T2	21559	21499	0	0
T3	39416	39366	0	0
T4	4093	3833	0	0
T5	916060	916009	0	0
T6	648946	648884	0	0
T7	481287	481280	0	0
T8	419502	419433	0	0
T9	809	738	0	0
T10	195664	195591	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461676998	461542423	0	0
T1	844	746	0	0
T2	21559	21499	0	0
T3	39416	39366	0	0
T4	4093	3833	0	0
T5	916060	916009	0	0
T6	648946	648884	0	0
T7	481287	481280	0	0
T8	419502	419433	0	0
T9	809	738	0	0
T10	195664	195591	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	461676998	6176569	0	0
DepthKnown_A	461676998	461542423	0	0
RvalidKnown_A	461676998	461542423	0	0
WreadyKnown_A	461676998	461542423	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461676998	6176569	0	0
T1	844	11	0	0
T2	21559	894	0	0
T3	39416	63	0	0
T4	4093	198	0	0
T5	916060	15503	0	0
T6	648946	15048	0	0
T7	481287	25641	0	0
T8	419502	31017	0	0
T9	809	16	0	0
T10	195664	255	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461676998	461542423	0	0
T1	844	746	0	0
T2	21559	21499	0	0
T3	39416	39366	0	0
T4	4093	3833	0	0
T5	916060	916009	0	0
T6	648946	648884	0	0
T7	481287	481280	0	0
T8	419502	419433	0	0
T9	809	738	0	0
T10	195664	195591	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461676998	461542423	0	0
T1	844	746	0	0
T2	21559	21499	0	0
T3	39416	39366	0	0
T4	4093	3833	0	0
T5	916060	916009	0	0
T6	648946	648884	0	0
T7	481287	481280	0	0
T8	419502	419433	0	0
T9	809	738	0	0
T10	195664	195591	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461676998	461542423	0	0
T1	844	746	0	0
T2	21559	21499	0	0
T3	39416	39366	0	0
T4	4093	3833	0	0
T5	916060	916009	0	0
T6	648946	648884	0	0
T7	481287	481280	0	0
T8	419502	419433	0	0
T9	809	738	0	0
T10	195664	195591	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	461676998	11630515	0	0
DepthKnown_A	461676998	461542423	0	0
RvalidKnown_A	461676998	461542423	0	0
WreadyKnown_A	461676998	461542423	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461676998	11630515	0	0
T1	844	11	0	0
T2	21559	3833	0	0
T3	39416	63	0	0
T4	4093	198	0	0
T5	916060	15455	0	0
T6	648946	46180	0	0
T7	481287	105139	0	0
T8	419502	31017	0	0
T9	809	16	0	0
T10	195664	255	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461676998	461542423	0	0
T1	844	746	0	0
T2	21559	21499	0	0
T3	39416	39366	0	0
T4	4093	3833	0	0
T5	916060	916009	0	0
T6	648946	648884	0	0
T7	481287	481280	0	0
T8	419502	419433	0	0
T9	809	738	0	0
T10	195664	195591	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461676998	461542423	0	0
T1	844	746	0	0
T2	21559	21499	0	0
T3	39416	39366	0	0
T4	4093	3833	0	0
T5	916060	916009	0	0
T6	648946	648884	0	0
T7	481287	481280	0	0
T8	419502	419433	0	0
T9	809	738	0	0
T10	195664	195591	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461676998	461542423	0	0
T1	844	746	0	0
T2	21559	21499	0	0
T3	39416	39366	0	0
T4	4093	3833	0	0
T5	916060	916009	0	0
T6	648946	648884	0	0
T7	481287	481280	0	0
T8	419502	419433	0	0
T9	809	738	0	0
T10	195664	195591	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0