Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T11
1	0	Covered	T5,T7,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T10
1	0	Unreachable
1	1	Covered	T5,T7,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T12
1	0	Covered	T5,T7,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Unreachable
1	1	Covered	T5,T7,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T11
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	746061881	601234045	0	0
CheckNGreaterZero_A	2925	2925	0	0
GntImpliesReady_A	746061881	3574535	0	0
GntImpliesValid_A	746061881	3574535	0	0
GrantKnown_A	746061881	601234045	0	0
IdxKnown_A	746061881	601234045	0	0
IndexIsCorrect_A	746061881	3574535	0	0
LockArbDecision_A	746061881	0	0	0
NoReadyValidNoGrant_A	746061881	0	0	0
ReadyAndValidImplyGrant_A	746061881	3574535	0	0
ReqAndReadyImplyGrant_A	746061881	3574535	0	0
ReqImpliesValid_A	746061881	3574535	0	0
ReqStaysHighUntilGranted0_M	746061881	0	0	0
RoundRobin_A	746061881	1	0	975
ValidKnown_A	746061881	601234045	0	0
gen_data_port_assertion.DataFlow_A	746061881	3574535	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746061881	601234045	0	0
T1	844	746	0	0
T2	76719	76659	0	0
T3	71565	71182	0	0
T4	4093	3833	0	0
T5	1141658	1025580	0	0
T6	833266	741044	0	0
T7	2375175	1426673	0	0
T8	523726	471545	0	0
T9	809	738	0	0
T10	246574	219167	0	0
T11	4650	2136	0	0
T12	1429108	711787	0	0
T13	34352	16966	0	0
T14	4112	4112	0	0
T15	1843	1843	0	0
T25	0	93040	0	0
T26	0	117160	0	0
T27	0	864	0	0
T28	0	3408	0	0
T29	0	326912	0	0
T30	0	42664	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2925	2925	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746061881	3574535	0	0
T2	21559	832	0	0
T3	39416	832	0	0
T4	4093	0	0	0
T5	1141658	5853	0	0
T6	833266	832	0	0
T7	2375175	15729	0	0
T8	523726	832	0	0
T9	809	0	0	0
T10	246574	0	0	0
T11	9445	168	0	0
T12	1429108	11508	0	0
T13	34352	832	0	0
T14	8224	832	0	0
T15	3686	0	0	0
T19	0	3143	0	0
T26	0	8931	0	0
T28	0	211	0	0
T29	0	19422	0	0
T30	0	2749	0	0
T37	0	4157	0	0
T38	0	1927	0	0
T41	0	1717	0	0
T45	0	136	0	0
T46	0	1028	0	0
T47	0	776	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746061881	3574535	0	0
T2	21559	832	0	0
T3	39416	832	0	0
T4	4093	0	0	0
T5	1141658	5853	0	0
T6	833266	832	0	0
T7	2375175	15729	0	0
T8	523726	832	0	0
T9	809	0	0	0
T10	246574	0	0	0
T11	9445	168	0	0
T12	1429108	11508	0	0
T13	34352	832	0	0
T14	8224	832	0	0
T15	3686	0	0	0
T19	0	3143	0	0
T26	0	8931	0	0
T28	0	211	0	0
T29	0	19422	0	0
T30	0	2749	0	0
T37	0	4157	0	0
T38	0	1927	0	0
T41	0	1717	0	0
T45	0	136	0	0
T46	0	1028	0	0
T47	0	776	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746061881	601234045	0	0
T1	844	746	0	0
T2	76719	76659	0	0
T3	71565	71182	0	0
T4	4093	3833	0	0
T5	1141658	1025580	0	0
T6	833266	741044	0	0
T7	2375175	1426673	0	0
T8	523726	471545	0	0
T9	809	738	0	0
T10	246574	219167	0	0
T11	4650	2136	0	0
T12	1429108	711787	0	0
T13	34352	16966	0	0
T14	4112	4112	0	0
T15	1843	1843	0	0
T25	0	93040	0	0
T26	0	117160	0	0
T27	0	864	0	0
T28	0	3408	0	0
T29	0	326912	0	0
T30	0	42664	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746061881	601234045	0	0
T1	844	746	0	0
T2	76719	76659	0	0
T3	71565	71182	0	0
T4	4093	3833	0	0
T5	1141658	1025580	0	0
T6	833266	741044	0	0
T7	2375175	1426673	0	0
T8	523726	471545	0	0
T9	809	738	0	0
T10	246574	219167	0	0
T11	4650	2136	0	0
T12	1429108	711787	0	0
T13	34352	16966	0	0
T14	4112	4112	0	0
T15	1843	1843	0	0
T25	0	93040	0	0
T26	0	117160	0	0
T27	0	864	0	0
T28	0	3408	0	0
T29	0	326912	0	0
T30	0	42664	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746061881	3574535	0	0
T2	21559	832	0	0
T3	39416	832	0	0
T4	4093	0	0	0
T5	1141658	5853	0	0
T6	833266	832	0	0
T7	2375175	15729	0	0
T8	523726	832	0	0
T9	809	0	0	0
T10	246574	0	0	0
T11	9445	168	0	0
T12	1429108	11508	0	0
T13	34352	832	0	0
T14	8224	832	0	0
T15	3686	0	0	0
T19	0	3143	0	0
T26	0	8931	0	0
T28	0	211	0	0
T29	0	19422	0	0
T30	0	2749	0	0
T37	0	4157	0	0
T38	0	1927	0	0
T41	0	1717	0	0
T45	0	136	0	0
T46	0	1028	0	0
T47	0	776	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746061881	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746061881	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746061881	3574535	0	0
T2	21559	832	0	0
T3	39416	832	0	0
T4	4093	0	0	0
T5	1141658	5853	0	0
T6	833266	832	0	0
T7	2375175	15729	0	0
T8	523726	832	0	0
T9	809	0	0	0
T10	246574	0	0	0
T11	9445	168	0	0
T12	1429108	11508	0	0
T13	34352	832	0	0
T14	8224	832	0	0
T15	3686	0	0	0
T19	0	3143	0	0
T26	0	8931	0	0
T28	0	211	0	0
T29	0	19422	0	0
T30	0	2749	0	0
T37	0	4157	0	0
T38	0	1927	0	0
T41	0	1717	0	0
T45	0	136	0	0
T46	0	1028	0	0
T47	0	776	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746061881	3574535	0	0
T2	21559	832	0	0
T3	39416	832	0	0
T4	4093	0	0	0
T5	1141658	5853	0	0
T6	833266	832	0	0
T7	2375175	15729	0	0
T8	523726	832	0	0
T9	809	0	0	0
T10	246574	0	0	0
T11	9445	168	0	0
T12	1429108	11508	0	0
T13	34352	832	0	0
T14	8224	832	0	0
T15	3686	0	0	0
T19	0	3143	0	0
T26	0	8931	0	0
T28	0	211	0	0
T29	0	19422	0	0
T30	0	2749	0	0
T37	0	4157	0	0
T38	0	1927	0	0
T41	0	1717	0	0
T45	0	136	0	0
T46	0	1028	0	0
T47	0	776	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746061881	3574535	0	0
T2	21559	832	0	0
T3	39416	832	0	0
T4	4093	0	0	0
T5	1141658	5853	0	0
T6	833266	832	0	0
T7	2375175	15729	0	0
T8	523726	832	0	0
T9	809	0	0	0
T10	246574	0	0	0
T11	9445	168	0	0
T12	1429108	11508	0	0
T13	34352	832	0	0
T14	8224	832	0	0
T15	3686	0	0	0
T19	0	3143	0	0
T26	0	8931	0	0
T28	0	211	0	0
T29	0	19422	0	0
T30	0	2749	0	0
T37	0	4157	0	0
T38	0	1927	0	0
T41	0	1717	0	0
T45	0	136	0	0
T46	0	1028	0	0
T47	0	776	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	746061881	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746061881	1	0	975
T16	4773	0	0	1
T29	162039	1	0	1
T38	227190	0	0	1
T40	10071	0	0	1
T48	10018	0	0	1
T49	13468	0	0	1
T50	154275	0	0	1
T51	1610	0	0	1
T52	839	0	0	1
T53	539493	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746061881	601234045	0	0
T1	844	746	0	0
T2	76719	76659	0	0
T3	71565	71182	0	0
T4	4093	3833	0	0
T5	1141658	1025580	0	0
T6	833266	741044	0	0
T7	2375175	1426673	0	0
T8	523726	471545	0	0
T9	809	738	0	0
T10	246574	219167	0	0
T11	4650	2136	0	0
T12	1429108	711787	0	0
T13	34352	16966	0	0
T14	4112	4112	0	0
T15	1843	1843	0	0
T25	0	93040	0	0
T26	0	117160	0	0
T27	0	864	0	0
T28	0	3408	0	0
T29	0	326912	0	0
T30	0	42664	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746061881	3574535	0	0
T2	21559	832	0	0
T3	39416	832	0	0
T4	4093	0	0	0
T5	1141658	5853	0	0
T6	833266	832	0	0
T7	2375175	15729	0	0
T8	523726	832	0	0
T9	809	0	0	0
T10	246574	0	0	0
T11	9445	168	0	0
T12	1429108	11508	0	0
T13	34352	832	0	0
T14	8224	832	0	0
T15	3686	0	0	0
T19	0	3143	0	0
T26	0	8931	0	0
T28	0	211	0	0
T29	0	19422	0	0
T30	0	2749	0	0
T37	0	4157	0	0
T38	0	1927	0	0
T41	0	1717	0	0
T45	0	136	0	0
T46	0	1028	0	0
T47	0	776	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T11
1	0	Covered	T5,T7,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T10
1	0	Unreachable
1	1	Covered	T5,T7,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T7,T11
0	0	1	Unreachable
0	0	0	Covered	T5,T7,T10

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	143408095	26058069	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	143408095	596165	0	0
GntImpliesValid_A	143408095	596165	0	0
GrantKnown_A	143408095	26058069	0	0
IdxKnown_A	143408095	26058069	0	0
IndexIsCorrect_A	143408095	596165	0	0
LockArbDecision_A	143408095	0	0	0
NoReadyValidNoGrant_A	143408095	0	0	0
ReadyAndValidImplyGrant_A	143408095	596165	0	0
ReqAndReadyImplyGrant_A	143408095	596165	0	0
ReqImpliesValid_A	143408095	596165	0	0
ReqStaysHighUntilGranted0_M	143408095	0	0	0
RoundRobin_A	143408095	0	0	0
ValidKnown_A	143408095	26058069	0	0
gen_data_port_assertion.DataFlow_A	143408095	596165	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	26058069	0	0
T5	112799	71992	0	0
T6	92160	0	0	0
T7	946944	17760	0	0
T8	52112	0	0	0
T10	25455	23576	0	0
T11	2325	2136	0	0
T12	714554	0	0	0
T13	17176	0	0	0
T14	4112	0	0	0
T15	1843	0	0	0
T25	0	93040	0	0
T26	0	117160	0	0
T27	0	864	0	0
T28	0	3408	0	0
T29	0	326912	0	0
T30	0	42664	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	596165	0	0
T5	112799	3462	0	0
T6	92160	0	0	0
T7	946944	584	0	0
T8	52112	0	0	0
T10	25455	0	0	0
T11	2325	124	0	0
T12	714554	0	0	0
T13	17176	0	0	0
T14	4112	0	0	0
T15	1843	0	0	0
T19	0	3143	0	0
T26	0	3706	0	0
T28	0	211	0	0
T29	0	8380	0	0
T30	0	1371	0	0
T41	0	1717	0	0
T45	0	136	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	596165	0	0
T5	112799	3462	0	0
T6	92160	0	0	0
T7	946944	584	0	0
T8	52112	0	0	0
T10	25455	0	0	0
T11	2325	124	0	0
T12	714554	0	0	0
T13	17176	0	0	0
T14	4112	0	0	0
T15	1843	0	0	0
T19	0	3143	0	0
T26	0	3706	0	0
T28	0	211	0	0
T29	0	8380	0	0
T30	0	1371	0	0
T41	0	1717	0	0
T45	0	136	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	26058069	0	0
T5	112799	71992	0	0
T6	92160	0	0	0
T7	946944	17760	0	0
T8	52112	0	0	0
T10	25455	23576	0	0
T11	2325	2136	0	0
T12	714554	0	0	0
T13	17176	0	0	0
T14	4112	0	0	0
T15	1843	0	0	0
T25	0	93040	0	0
T26	0	117160	0	0
T27	0	864	0	0
T28	0	3408	0	0
T29	0	326912	0	0
T30	0	42664	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	26058069	0	0
T5	112799	71992	0	0
T6	92160	0	0	0
T7	946944	17760	0	0
T8	52112	0	0	0
T10	25455	23576	0	0
T11	2325	2136	0	0
T12	714554	0	0	0
T13	17176	0	0	0
T14	4112	0	0	0
T15	1843	0	0	0
T25	0	93040	0	0
T26	0	117160	0	0
T27	0	864	0	0
T28	0	3408	0	0
T29	0	326912	0	0
T30	0	42664	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	596165	0	0
T5	112799	3462	0	0
T6	92160	0	0	0
T7	946944	584	0	0
T8	52112	0	0	0
T10	25455	0	0	0
T11	2325	124	0	0
T12	714554	0	0	0
T13	17176	0	0	0
T14	4112	0	0	0
T15	1843	0	0	0
T19	0	3143	0	0
T26	0	3706	0	0
T28	0	211	0	0
T29	0	8380	0	0
T30	0	1371	0	0
T41	0	1717	0	0
T45	0	136	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	596165	0	0
T5	112799	3462	0	0
T6	92160	0	0	0
T7	946944	584	0	0
T8	52112	0	0	0
T10	25455	0	0	0
T11	2325	124	0	0
T12	714554	0	0	0
T13	17176	0	0	0
T14	4112	0	0	0
T15	1843	0	0	0
T19	0	3143	0	0
T26	0	3706	0	0
T28	0	211	0	0
T29	0	8380	0	0
T30	0	1371	0	0
T41	0	1717	0	0
T45	0	136	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	596165	0	0
T5	112799	3462	0	0
T6	92160	0	0	0
T7	946944	584	0	0
T8	52112	0	0	0
T10	25455	0	0	0
T11	2325	124	0	0
T12	714554	0	0	0
T13	17176	0	0	0
T14	4112	0	0	0
T15	1843	0	0	0
T19	0	3143	0	0
T26	0	3706	0	0
T28	0	211	0	0
T29	0	8380	0	0
T30	0	1371	0	0
T41	0	1717	0	0
T45	0	136	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	596165	0	0
T5	112799	3462	0	0
T6	92160	0	0	0
T7	946944	584	0	0
T8	52112	0	0	0
T10	25455	0	0	0
T11	2325	124	0	0
T12	714554	0	0	0
T13	17176	0	0	0
T14	4112	0	0	0
T15	1843	0	0	0
T19	0	3143	0	0
T26	0	3706	0	0
T28	0	211	0	0
T29	0	8380	0	0
T30	0	1371	0	0
T41	0	1717	0	0
T45	0	136	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	26058069	0	0
T5	112799	71992	0	0
T6	92160	0	0	0
T7	946944	17760	0	0
T8	52112	0	0	0
T10	25455	23576	0	0
T11	2325	2136	0	0
T12	714554	0	0	0
T13	17176	0	0	0
T14	4112	0	0	0
T15	1843	0	0	0
T25	0	93040	0	0
T26	0	117160	0	0
T27	0	864	0	0
T28	0	3408	0	0
T29	0	326912	0	0
T30	0	42664	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	596165	0	0
T5	112799	3462	0	0
T6	92160	0	0	0
T7	946944	584	0	0
T8	52112	0	0	0
T10	25455	0	0	0
T11	2325	124	0	0
T12	714554	0	0	0
T13	17176	0	0	0
T14	4112	0	0	0
T15	1843	0	0	0
T19	0	3143	0	0
T26	0	3706	0	0
T28	0	211	0	0
T29	0	8380	0	0
T30	0	1371	0	0
T41	0	1717	0	0
T45	0	136	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T12
1	0	Covered	T5,T7,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Unreachable
1	1	Covered	T5,T7,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T7,T12
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	143408095	116019277	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	143408095	763389	0	0
GntImpliesValid_A	143408095	763389	0	0
GrantKnown_A	143408095	116019277	0	0
IdxKnown_A	143408095	116019277	0	0
IndexIsCorrect_A	143408095	763389	0	0
LockArbDecision_A	143408095	0	0	0
NoReadyValidNoGrant_A	143408095	0	0	0
ReadyAndValidImplyGrant_A	143408095	763389	0	0
ReqAndReadyImplyGrant_A	143408095	763389	0	0
ReqImpliesValid_A	143408095	763389	0	0
ReqStaysHighUntilGranted0_M	143408095	0	0	0
RoundRobin_A	143408095	0	0	0
ValidKnown_A	143408095	116019277	0	0
gen_data_port_assertion.DataFlow_A	143408095	763389	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	116019277	0	0
T2	55160	55160	0	0
T3	32149	31816	0	0
T5	112799	37579	0	0
T6	92160	92160	0	0
T7	946944	927633	0	0
T8	52112	52112	0	0
T10	25455	0	0	0
T11	2325	0	0	0
T12	714554	711787	0	0
T13	17176	16966	0	0
T14	0	4112	0	0
T15	0	1843	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	763389	0	0
T5	112799	2	0	0
T6	92160	0	0	0
T7	946944	3722	0	0
T8	52112	0	0	0
T10	25455	0	0	0
T11	2325	0	0	0
T12	714554	1203	0	0
T13	17176	0	0	0
T14	4112	0	0	0
T15	1843	0	0	0
T26	0	5225	0	0
T29	0	11042	0	0
T30	0	1378	0	0
T37	0	4157	0	0
T38	0	1927	0	0
T46	0	1028	0	0
T47	0	776	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	763389	0	0
T5	112799	2	0	0
T6	92160	0	0	0
T7	946944	3722	0	0
T8	52112	0	0	0
T10	25455	0	0	0
T11	2325	0	0	0
T12	714554	1203	0	0
T13	17176	0	0	0
T14	4112	0	0	0
T15	1843	0	0	0
T26	0	5225	0	0
T29	0	11042	0	0
T30	0	1378	0	0
T37	0	4157	0	0
T38	0	1927	0	0
T46	0	1028	0	0
T47	0	776	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	116019277	0	0
T2	55160	55160	0	0
T3	32149	31816	0	0
T5	112799	37579	0	0
T6	92160	92160	0	0
T7	946944	927633	0	0
T8	52112	52112	0	0
T10	25455	0	0	0
T11	2325	0	0	0
T12	714554	711787	0	0
T13	17176	16966	0	0
T14	0	4112	0	0
T15	0	1843	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	116019277	0	0
T2	55160	55160	0	0
T3	32149	31816	0	0
T5	112799	37579	0	0
T6	92160	92160	0	0
T7	946944	927633	0	0
T8	52112	52112	0	0
T10	25455	0	0	0
T11	2325	0	0	0
T12	714554	711787	0	0
T13	17176	16966	0	0
T14	0	4112	0	0
T15	0	1843	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	763389	0	0
T5	112799	2	0	0
T6	92160	0	0	0
T7	946944	3722	0	0
T8	52112	0	0	0
T10	25455	0	0	0
T11	2325	0	0	0
T12	714554	1203	0	0
T13	17176	0	0	0
T14	4112	0	0	0
T15	1843	0	0	0
T26	0	5225	0	0
T29	0	11042	0	0
T30	0	1378	0	0
T37	0	4157	0	0
T38	0	1927	0	0
T46	0	1028	0	0
T47	0	776	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	763389	0	0
T5	112799	2	0	0
T6	92160	0	0	0
T7	946944	3722	0	0
T8	52112	0	0	0
T10	25455	0	0	0
T11	2325	0	0	0
T12	714554	1203	0	0
T13	17176	0	0	0
T14	4112	0	0	0
T15	1843	0	0	0
T26	0	5225	0	0
T29	0	11042	0	0
T30	0	1378	0	0
T37	0	4157	0	0
T38	0	1927	0	0
T46	0	1028	0	0
T47	0	776	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	763389	0	0
T5	112799	2	0	0
T6	92160	0	0	0
T7	946944	3722	0	0
T8	52112	0	0	0
T10	25455	0	0	0
T11	2325	0	0	0
T12	714554	1203	0	0
T13	17176	0	0	0
T14	4112	0	0	0
T15	1843	0	0	0
T26	0	5225	0	0
T29	0	11042	0	0
T30	0	1378	0	0
T37	0	4157	0	0
T38	0	1927	0	0
T46	0	1028	0	0
T47	0	776	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	763389	0	0
T5	112799	2	0	0
T6	92160	0	0	0
T7	946944	3722	0	0
T8	52112	0	0	0
T10	25455	0	0	0
T11	2325	0	0	0
T12	714554	1203	0	0
T13	17176	0	0	0
T14	4112	0	0	0
T15	1843	0	0	0
T26	0	5225	0	0
T29	0	11042	0	0
T30	0	1378	0	0
T37	0	4157	0	0
T38	0	1927	0	0
T46	0	1028	0	0
T47	0	776	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	116019277	0	0
T2	55160	55160	0	0
T3	32149	31816	0	0
T5	112799	37579	0	0
T6	92160	92160	0	0
T7	946944	927633	0	0
T8	52112	52112	0	0
T10	25455	0	0	0
T11	2325	0	0	0
T12	714554	711787	0	0
T13	17176	16966	0	0
T14	0	4112	0	0
T15	0	1843	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143408095	763389	0	0
T5	112799	2	0	0
T6	92160	0	0	0
T7	946944	3722	0	0
T8	52112	0	0	0
T10	25455	0	0	0
T11	2325	0	0	0
T12	714554	1203	0	0
T13	17176	0	0	0
T14	4112	0	0	0
T15	1843	0	0	0
T26	0	5225	0	0
T29	0	11042	0	0
T30	0	1378	0	0
T37	0	4157	0	0
T38	0	1927	0	0
T46	0	1028	0	0
T47	0	776	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T11
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	459245691	459156699	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	459245691	2214981	0	0
GntImpliesValid_A	459245691	2214981	0	0
GrantKnown_A	459245691	459156699	0	0
IdxKnown_A	459245691	459156699	0	0
IndexIsCorrect_A	459245691	2214981	0	0
LockArbDecision_A	459245691	0	0	0
NoReadyValidNoGrant_A	459245691	0	0	0
ReadyAndValidImplyGrant_A	459245691	2214981	0	0
ReqAndReadyImplyGrant_A	459245691	2214981	0	0
ReqImpliesValid_A	459245691	2214981	0	0
ReqStaysHighUntilGranted0_M	459245691	0	0	0
RoundRobin_A	459245691	1	0	975
ValidKnown_A	459245691	459156699	0	0
gen_data_port_assertion.DataFlow_A	459245691	2214981	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459245691	459156699	0	0
T1	844	746	0	0
T2	21559	21499	0	0
T3	39416	39366	0	0
T4	4093	3833	0	0
T5	916060	916009	0	0
T6	648946	648884	0	0
T7	481287	481280	0	0
T8	419502	419433	0	0
T9	809	738	0	0
T10	195664	195591	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459245691	2214981	0	0
T2	21559	832	0	0
T3	39416	832	0	0
T4	4093	0	0	0
T5	916060	2389	0	0
T6	648946	832	0	0
T7	481287	11423	0	0
T8	419502	832	0	0
T9	809	0	0	0
T10	195664	0	0	0
T11	4795	44	0	0
T12	0	10305	0	0
T13	0	832	0	0
T14	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459245691	2214981	0	0
T2	21559	832	0	0
T3	39416	832	0	0
T4	4093	0	0	0
T5	916060	2389	0	0
T6	648946	832	0	0
T7	481287	11423	0	0
T8	419502	832	0	0
T9	809	0	0	0
T10	195664	0	0	0
T11	4795	44	0	0
T12	0	10305	0	0
T13	0	832	0	0
T14	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459245691	459156699	0	0
T1	844	746	0	0
T2	21559	21499	0	0
T3	39416	39366	0	0
T4	4093	3833	0	0
T5	916060	916009	0	0
T6	648946	648884	0	0
T7	481287	481280	0	0
T8	419502	419433	0	0
T9	809	738	0	0
T10	195664	195591	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459245691	459156699	0	0
T1	844	746	0	0
T2	21559	21499	0	0
T3	39416	39366	0	0
T4	4093	3833	0	0
T5	916060	916009	0	0
T6	648946	648884	0	0
T7	481287	481280	0	0
T8	419502	419433	0	0
T9	809	738	0	0
T10	195664	195591	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459245691	2214981	0	0
T2	21559	832	0	0
T3	39416	832	0	0
T4	4093	0	0	0
T5	916060	2389	0	0
T6	648946	832	0	0
T7	481287	11423	0	0
T8	419502	832	0	0
T9	809	0	0	0
T10	195664	0	0	0
T11	4795	44	0	0
T12	0	10305	0	0
T13	0	832	0	0
T14	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459245691	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459245691	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459245691	2214981	0	0
T2	21559	832	0	0
T3	39416	832	0	0
T4	4093	0	0	0
T5	916060	2389	0	0
T6	648946	832	0	0
T7	481287	11423	0	0
T8	419502	832	0	0
T9	809	0	0	0
T10	195664	0	0	0
T11	4795	44	0	0
T12	0	10305	0	0
T13	0	832	0	0
T14	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459245691	2214981	0	0
T2	21559	832	0	0
T3	39416	832	0	0
T4	4093	0	0	0
T5	916060	2389	0	0
T6	648946	832	0	0
T7	481287	11423	0	0
T8	419502	832	0	0
T9	809	0	0	0
T10	195664	0	0	0
T11	4795	44	0	0
T12	0	10305	0	0
T13	0	832	0	0
T14	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459245691	2214981	0	0
T2	21559	832	0	0
T3	39416	832	0	0
T4	4093	0	0	0
T5	916060	2389	0	0
T6	648946	832	0	0
T7	481287	11423	0	0
T8	419502	832	0	0
T9	809	0	0	0
T10	195664	0	0	0
T11	4795	44	0	0
T12	0	10305	0	0
T13	0	832	0	0
T14	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	459245691	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459245691	1	0	975
T16	4773	0	0	1
T29	162039	1	0	1
T38	227190	0	0	1
T40	10071	0	0	1
T48	10018	0	0	1
T49	13468	0	0	1
T50	154275	0	0	1
T51	1610	0	0	1
T52	839	0	0	1
T53	539493	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459245691	459156699	0	0
T1	844	746	0	0
T2	21559	21499	0	0
T3	39416	39366	0	0
T4	4093	3833	0	0
T5	916060	916009	0	0
T6	648946	648884	0	0
T7	481287	481280	0	0
T8	419502	419433	0	0
T9	809	738	0	0
T10	195664	195591	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459245691	2214981	0	0
T2	21559	832	0	0
T3	39416	832	0	0
T4	4093	0	0	0
T5	916060	2389	0	0
T6	648946	832	0	0
T7	481287	11423	0	0
T8	419502	832	0	0
T9	809	0	0	0
T10	195664	0	0	0
T11	4795	44	0	0
T12	0	10305	0	0
T13	0	832	0	0
T14	0	832	0	0