Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3631072	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4291655

1

T1

878

T2

2

T3

1218

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4297144	1			T1	3		T2	1		T3	565
values[0x0]	1811158	1			T1	419		T2	6		T3	447
values[0x1]	1814425	1			T1	458		T2	4		T3	442

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2572092	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5350635

1

T1

878

T2

3

T3

1262

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	31096	1			T1	5		T4	122		T8	1
valid_sources[0x01]	29810	1			T1	5		T4	477		T6	1
valid_sources[0x02]	29128	1			T1	2		T4	358		T8	7
valid_sources[0x03]	29343	1			T1	9		T4	804		T6	1
valid_sources[0x04]	29965	1			T1	3		T4	517		T9	169
valid_sources[0x05]	33908	1			T1	3		T3	3		T4	341
valid_sources[0x06]	33030	1			T1	1		T4	769		T8	6
valid_sources[0x07]	30254	1			T1	11		T4	1119		T8	1
valid_sources[0x08]	29927	1			T1	8		T4	779		T8	8
valid_sources[0x09]	29810	1			T1	3		T4	515		T9	193
valid_sources[0x0a]	28031	1			T1	6		T4	312		T8	5
valid_sources[0x0b]	34859	1			T1	2		T4	708		T6	1
valid_sources[0x0c]	28331	1			T4	175		T9	165		T11	99
valid_sources[0x0d]	31411	1			T1	3		T4	294		T8	1
valid_sources[0x0e]	32802	1			T1	6		T3	1		T4	450
valid_sources[0x0f]	33431	1			T1	6		T4	442		T8	2
valid_sources[0x10]	29418	1			T1	1		T3	1		T4	320
valid_sources[0x11]	28817	1			T1	1		T4	138		T7	4
valid_sources[0x12]	27834	1			T1	6		T4	164		T9	168
valid_sources[0x13]	29633	1			T1	2		T4	526		T8	2
valid_sources[0x14]	30447	1			T1	2		T4	224		T8	6
valid_sources[0x15]	30106	1			T1	1		T3	1		T4	530
valid_sources[0x16]	31382	1			T1	2		T4	245		T8	4
valid_sources[0x17]	27753	1			T1	4		T4	345		T8	3
valid_sources[0x18]	32124	1			T1	12		T4	465		T9	151
valid_sources[0x19]	32485	1			T1	3		T4	431		T8	1
valid_sources[0x1a]	31343	1			T4	166		T8	3		T9	153
valid_sources[0x1b]	31434	1			T4	84		T6	1		T9	172
valid_sources[0x1c]	32914	1			T1	3		T4	357		T8	5
valid_sources[0x1d]	29983	1			T1	3		T4	786		T8	3
valid_sources[0x1e]	29481	1			T1	4		T4	299		T8	1
valid_sources[0x1f]	31094	1			T1	2		T4	390		T8	2
valid_sources[0x20]	38704	1			T1	8		T4	567		T6	1
valid_sources[0x21]	30048	1			T1	4		T4	243		T8	2
valid_sources[0x22]	31004	1			T1	4		T4	99		T8	4
valid_sources[0x23]	29142	1			T1	6		T4	537		T6	1
valid_sources[0x24]	28930	1			T1	3		T4	150		T8	2
valid_sources[0x25]	26502	1			T1	5		T4	421		T6	1
valid_sources[0x26]	29001	1			T1	1		T4	359		T8	13
valid_sources[0x27]	31928	1			T1	2		T3	1		T4	569
valid_sources[0x28]	28112	1			T1	2		T4	410		T8	5
valid_sources[0x29]	28380	1			T1	6		T3	159		T4	291
valid_sources[0x2a]	39359	1			T1	4		T4	169		T8	4
valid_sources[0x2b]	26930	1			T1	1		T4	368		T6	2
valid_sources[0x2c]	29399	1			T1	2		T4	310		T6	2
valid_sources[0x2d]	32229	1			T1	2		T4	569		T8	1
valid_sources[0x2e]	29353	1			T3	97		T4	384		T8	1
valid_sources[0x2f]	31946	1			T4	410		T8	6		T9	210
valid_sources[0x30]	33286	1			T1	1		T4	733		T8	1
valid_sources[0x31]	30971	1			T1	2		T4	426		T8	2
valid_sources[0x32]	29618	1			T1	3		T4	935		T8	4
valid_sources[0x33]	29891	1			T1	14		T4	447		T8	1
valid_sources[0x34]	30211	1			T1	6		T4	63		T8	4
valid_sources[0x35]	39181	1			T1	2		T4	233		T8	4
valid_sources[0x36]	28421	1			T1	1		T4	249		T8	6
valid_sources[0x37]	31655	1			T1	2		T4	448		T6	2
valid_sources[0x38]	29192	1			T1	3		T3	70		T4	175
valid_sources[0x39]	29401	1			T1	4		T4	286		T8	10
valid_sources[0x3a]	30295	1			T1	5		T4	209		T8	4
valid_sources[0x3b]	29413	1			T1	7		T4	262		T6	1
valid_sources[0x3c]	30885	1			T1	4		T4	543		T8	4
valid_sources[0x3d]	33524	1			T1	2		T4	193		T8	3
valid_sources[0x3e]	30036	1			T1	5		T4	755		T8	2
valid_sources[0x3f]	28112	1			T1	4		T4	476		T6	1
valid_sources[0x40]	28300	1			T1	2		T4	513		T9	156
valid_sources[0x41]	34541	1			T1	3		T4	395		T6	2
valid_sources[0x42]	31400	1			T4	496		T8	2		T9	168
valid_sources[0x43]	35737	1			T1	4		T3	1		T4	202
valid_sources[0x44]	31180	1			T1	4		T4	1417		T8	6
valid_sources[0x45]	31337	1			T1	3		T4	1043		T8	3
valid_sources[0x46]	30702	1			T1	1		T4	376		T6	1
valid_sources[0x47]	26031	1			T4	509		T8	4		T9	180
valid_sources[0x48]	31178	1			T1	3		T4	487		T9	136
valid_sources[0x49]	30054	1			T1	1		T4	727		T8	5
valid_sources[0x4a]	31046	1			T1	6		T4	360		T8	2
valid_sources[0x4b]	30490	1			T1	4		T4	217		T8	22
valid_sources[0x4c]	32793	1			T1	3		T4	90		T9	153
valid_sources[0x4d]	29034	1			T1	6		T4	440		T8	4
valid_sources[0x4e]	30056	1			T1	2		T3	3		T4	443
valid_sources[0x4f]	31085	1			T4	112		T8	4		T9	167
valid_sources[0x50]	31029	1			T1	7		T4	75		T8	1
valid_sources[0x51]	28805	1			T1	1		T4	174		T8	1
valid_sources[0x52]	31674	1			T1	5		T4	546		T8	1
valid_sources[0x53]	27284	1			T1	6		T4	131		T8	3
valid_sources[0x54]	28418	1			T1	2		T4	777		T8	3
valid_sources[0x55]	33712	1			T1	5		T4	256		T6	1
valid_sources[0x56]	30470	1			T1	5		T4	297		T7	1015
valid_sources[0x57]	30271	1			T1	4		T3	1		T4	1083
valid_sources[0x58]	29308	1			T1	5		T4	279		T8	5
valid_sources[0x59]	28990	1			T4	231		T6	2		T8	3
valid_sources[0x5a]	30701	1			T1	1		T4	363		T8	5
valid_sources[0x5b]	34407	1			T1	2		T4	555		T8	1
valid_sources[0x5c]	29409	1			T1	4		T4	497		T8	5
valid_sources[0x5d]	31669	1			T1	10		T4	878		T8	3
valid_sources[0x5e]	28739	1			T1	7		T4	606		T8	7
valid_sources[0x5f]	29811	1			T1	3		T4	703		T8	7
valid_sources[0x60]	30197	1			T1	3		T4	345		T8	3
valid_sources[0x61]	28388	1			T1	7		T3	1		T4	304
valid_sources[0x62]	28387	1			T3	1		T4	355		T8	8
valid_sources[0x63]	28466	1			T1	5		T4	559		T6	1
valid_sources[0x64]	27049	1			T1	9		T4	52		T8	2
valid_sources[0x65]	30585	1			T4	329		T8	4		T9	163
valid_sources[0x66]	38036	1			T4	260		T8	2		T9	154
valid_sources[0x67]	28964	1			T1	4		T4	161		T8	4
valid_sources[0x68]	30951	1			T4	137		T6	1		T8	1
valid_sources[0x69]	31039	1			T1	5		T4	488		T8	2
valid_sources[0x6a]	47957	1			T1	1		T4	244		T6	1
valid_sources[0x6b]	29071	1			T1	2		T4	461		T8	1
valid_sources[0x6c]	29990	1			T1	2		T4	583		T8	1
valid_sources[0x6d]	29251	1			T1	4		T4	96		T8	2
valid_sources[0x6e]	30009	1			T1	7		T4	277		T9	171
valid_sources[0x6f]	28761	1			T1	3		T4	457		T8	6
valid_sources[0x70]	40661	1			T1	5		T4	293		T8	4
valid_sources[0x71]	31269	1			T1	2		T4	382		T6	2
valid_sources[0x72]	32605	1			T1	7		T4	1227		T6	1
valid_sources[0x73]	31932	1			T1	1		T3	1		T4	444
valid_sources[0x74]	31815	1			T1	4		T4	158		T8	1
valid_sources[0x75]	29352	1			T4	462		T8	1		T9	154
valid_sources[0x76]	34570	1			T1	12		T4	565		T8	4
valid_sources[0x77]	30406	1			T1	8		T4	109		T6	1
valid_sources[0x78]	28687	1			T1	1		T4	491		T9	175
valid_sources[0x79]	31532	1			T1	3		T4	612		T8	6
valid_sources[0x7a]	32502	1			T1	3		T4	277		T6	1
valid_sources[0x7b]	28319	1			T1	3		T3	1		T4	620
valid_sources[0x7c]	28908	1			T1	5		T4	669		T8	1
valid_sources[0x7d]	35844	1			T1	4		T4	798		T8	1
valid_sources[0x7e]	28360	1			T1	7		T4	273		T9	132
valid_sources[0x7f]	33627	1			T1	14		T4	572		T8	9
valid_sources[0x80]	30040	1			T1	4		T4	659		T8	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1020411

1

T1

3

T3

336

T4

5379

values[0x0]

all_enables

biggest_size

1647585

1

T1

418

T2

2

T3

442

values[0x1]

all_enables

biggest_size

1623659

1

T1

457

T3

440

T4

18318