Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3655326

1

T1

2

T2

9

T3

236

full_word

4290977

1

T1

878

T2

2

T3

1218

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7945913	1			T1	880		T2	11		T3	1454
auto[TlIntgErrCmd]	128	1			T93	1		T95	10		T96	3
auto[TlIntgErrData]	142	1			T93	3		T95	10		T96	12
auto[TlIntgErrBoth]	120	1			T93	6		T95	10		T96	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4300953

1

T1

3

T2

1

T3

565

auto[1]

3645350

1

T1

877

T2

10

T3

889

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3280185	1			T2	1		T3	229		T4	57923
auto[TlIntgErrNone]	partial	auto[1]	374787	1			T1	2		T2	8		T3	7
auto[TlIntgErrNone]	full_word	auto[0]	1020601	1			T1	3		T3	336		T4	5379
auto[TlIntgErrNone]	full_word	auto[1]	3270340	1			T1	875		T2	2		T3	882
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T93	1		T95	4		T96	2
auto[TlIntgErrCmd]	partial	auto[1]	73	1			T95	5		T96	1		T166	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T95	1		T167	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T168	1		T169	1		T170	1
auto[TlIntgErrData]	partial	auto[0]	63	1			T93	1		T95	7		T96	6
auto[TlIntgErrData]	partial	auto[1]	62	1			T93	1		T95	2		T96	6
auto[TlIntgErrData]	full_word	auto[0]	8	1			T93	1		T166	2		T167	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T95	1		T111	1		T167	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T93	1		T95	3		T96	2
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T93	4		T95	4		T96	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T111	1		T171	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T93	1		T95	3		T96	1