Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	445284861	2877541	0	0
DepthKnown_A	445284861	445153043	0	0
RvalidKnown_A	445284861	445153043	0	0
WreadyKnown_A	445284861	445153043	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	2877541	0	0
T1	20098	1663	0	0
T2	2099	0	0	0
T3	336889	832	0	0
T4	557141	18296	0	0
T5	938	0	0	0
T6	1360	0	0	0
T7	15206	832	0	0
T8	440701	832	0	0
T9	249066	19998	0	0
T10	196026	1663	0	0
T11	0	1664	0	0
T14	0	7497	0	0
T15	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	445153043	0	0
T1	20098	20037	0	0
T2	2099	2027	0	0
T3	336889	336814	0	0
T4	557141	557106	0	0
T5	938	845	0	0
T6	1360	1280	0	0
T7	15206	15147	0	0
T8	440701	440642	0	0
T9	249066	249060	0	0
T10	196026	195968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	445153043	0	0
T1	20098	20037	0	0
T2	2099	2027	0	0
T3	336889	336814	0	0
T4	557141	557106	0	0
T5	938	845	0	0
T6	1360	1280	0	0
T7	15206	15147	0	0
T8	440701	440642	0	0
T9	249066	249060	0	0
T10	196026	195968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	445153043	0	0
T1	20098	20037	0	0
T2	2099	2027	0	0
T3	336889	336814	0	0
T4	557141	557106	0	0
T5	938	845	0	0
T6	1360	1280	0	0
T7	15206	15147	0	0
T8	440701	440642	0	0
T9	249066	249060	0	0
T10	196026	195968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	445284861	3320682	0	0
DepthKnown_A	445284861	445153043	0	0
RvalidKnown_A	445284861	445153043	0	0
WreadyKnown_A	445284861	445153043	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	3320682	0	0
T1	20098	832	0	0
T2	2099	0	0	0
T3	336889	3777	0	0
T4	557141	11648	0	0
T5	938	0	0	0
T6	1360	0	0	0
T7	15206	3782	0	0
T8	440701	832	0	0
T9	249066	23836	0	0
T10	196026	832	0	0
T11	0	1664	0	0
T14	0	10902	0	0
T15	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	445153043	0	0
T1	20098	20037	0	0
T2	2099	2027	0	0
T3	336889	336814	0	0
T4	557141	557106	0	0
T5	938	845	0	0
T6	1360	1280	0	0
T7	15206	15147	0	0
T8	440701	440642	0	0
T9	249066	249060	0	0
T10	196026	195968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	445153043	0	0
T1	20098	20037	0	0
T2	2099	2027	0	0
T3	336889	336814	0	0
T4	557141	557106	0	0
T5	938	845	0	0
T6	1360	1280	0	0
T7	15206	15147	0	0
T8	440701	440642	0	0
T9	249066	249060	0	0
T10	196026	195968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	445153043	0	0
T1	20098	20037	0	0
T2	2099	2027	0	0
T3	336889	336814	0	0
T4	557141	557106	0	0
T5	938	845	0	0
T6	1360	1280	0	0
T7	15206	15147	0	0
T8	440701	440642	0	0
T9	249066	249060	0	0
T10	196026	195968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	445284861	215170	0	0
DepthKnown_A	445284861	445153043	0	0
RvalidKnown_A	445284861	445153043	0	0
WreadyKnown_A	445284861	445153043	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	215170	0	0
T3	336889	96	0	0
T4	557141	1254	0	0
T5	938	0	0	0
T6	1360	0	0	0
T7	15206	0	0	0
T8	440701	0	0	0
T9	249066	466	0	0
T10	196026	0	0	0
T11	104460	989	0	0
T12	223876	0	0	0
T14	0	1500	0	0
T16	0	2168	0	0
T24	0	943	0	0
T26	0	578	0	0
T35	0	384	0	0
T36	0	354	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	445153043	0	0
T1	20098	20037	0	0
T2	2099	2027	0	0
T3	336889	336814	0	0
T4	557141	557106	0	0
T5	938	845	0	0
T6	1360	1280	0	0
T7	15206	15147	0	0
T8	440701	440642	0	0
T9	249066	249060	0	0
T10	196026	195968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	445153043	0	0
T1	20098	20037	0	0
T2	2099	2027	0	0
T3	336889	336814	0	0
T4	557141	557106	0	0
T5	938	845	0	0
T6	1360	1280	0	0
T7	15206	15147	0	0
T8	440701	440642	0	0
T9	249066	249060	0	0
T10	196026	195968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	445153043	0	0
T1	20098	20037	0	0
T2	2099	2027	0	0
T3	336889	336814	0	0
T4	557141	557106	0	0
T5	938	845	0	0
T6	1360	1280	0	0
T7	15206	15147	0	0
T8	440701	440642	0	0
T9	249066	249060	0	0
T10	196026	195968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	445284861	501679	0	0
DepthKnown_A	445284861	445153043	0	0
RvalidKnown_A	445284861	445153043	0	0
WreadyKnown_A	445284861	445153043	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	501679	0	0
T3	336889	434	0	0
T4	557141	1254	0	0
T5	938	0	0	0
T6	1360	0	0	0
T7	15206	0	0	0
T8	440701	0	0	0
T9	249066	2166	0	0
T10	196026	0	0	0
T11	104460	989	0	0
T12	223876	0	0	0
T14	0	6346	0	0
T16	0	9739	0	0
T24	0	4189	0	0
T26	0	578	0	0
T35	0	1792	0	0
T36	0	354	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	445153043	0	0
T1	20098	20037	0	0
T2	2099	2027	0	0
T3	336889	336814	0	0
T4	557141	557106	0	0
T5	938	845	0	0
T6	1360	1280	0	0
T7	15206	15147	0	0
T8	440701	440642	0	0
T9	249066	249060	0	0
T10	196026	195968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	445153043	0	0
T1	20098	20037	0	0
T2	2099	2027	0	0
T3	336889	336814	0	0
T4	557141	557106	0	0
T5	938	845	0	0
T6	1360	1280	0	0
T7	15206	15147	0	0
T8	440701	440642	0	0
T9	249066	249060	0	0
T10	196026	195968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	445153043	0	0
T1	20098	20037	0	0
T2	2099	2027	0	0
T3	336889	336814	0	0
T4	557141	557106	0	0
T5	938	845	0	0
T6	1360	1280	0	0
T7	15206	15147	0	0
T8	440701	440642	0	0
T9	249066	249060	0	0
T10	196026	195968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	445284861	6255991	0	0
DepthKnown_A	445284861	445153043	0	0
RvalidKnown_A	445284861	445153043	0	0
WreadyKnown_A	445284861	445153043	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	6255991	0	0
T1	20098	48	0	0
T2	2099	11	0	0
T3	336889	530	0	0
T4	557141	93885	0	0
T5	938	12	0	0
T6	1360	71	0	0
T7	15206	188	0	0
T8	440701	53	0	0
T9	249066	34567	0	0
T10	196026	376	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	445153043	0	0
T1	20098	20037	0	0
T2	2099	2027	0	0
T3	336889	336814	0	0
T4	557141	557106	0	0
T5	938	845	0	0
T6	1360	1280	0	0
T7	15206	15147	0	0
T8	440701	440642	0	0
T9	249066	249060	0	0
T10	196026	195968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	445153043	0	0
T1	20098	20037	0	0
T2	2099	2027	0	0
T3	336889	336814	0	0
T4	557141	557106	0	0
T5	938	845	0	0
T6	1360	1280	0	0
T7	15206	15147	0	0
T8	440701	440642	0	0
T9	249066	249060	0	0
T10	196026	195968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	445153043	0	0
T1	20098	20037	0	0
T2	2099	2027	0	0
T3	336889	336814	0	0
T4	557141	557106	0	0
T5	938	845	0	0
T6	1360	1280	0	0
T7	15206	15147	0	0
T8	440701	440642	0	0
T9	249066	249060	0	0
T10	196026	195968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	445284861	13770438	0	0
DepthKnown_A	445284861	445153043	0	0
RvalidKnown_A	445284861	445153043	0	0
WreadyKnown_A	445284861	445153043	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	13770438	0	0
T1	20098	124	0	0
T2	2099	11	0	0
T3	336889	2345	0	0
T4	557141	93371	0	0
T5	938	54	0	0
T6	1360	71	0	0
T7	15206	793	0	0
T8	440701	53	0	0
T9	249066	137581	0	0
T10	196026	376	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	445153043	0	0
T1	20098	20037	0	0
T2	2099	2027	0	0
T3	336889	336814	0	0
T4	557141	557106	0	0
T5	938	845	0	0
T6	1360	1280	0	0
T7	15206	15147	0	0
T8	440701	440642	0	0
T9	249066	249060	0	0
T10	196026	195968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	445153043	0	0
T1	20098	20037	0	0
T2	2099	2027	0	0
T3	336889	336814	0	0
T4	557141	557106	0	0
T5	938	845	0	0
T6	1360	1280	0	0
T7	15206	15147	0	0
T8	440701	440642	0	0
T9	249066	249060	0	0
T10	196026	195968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	445153043	0	0
T1	20098	20037	0	0
T2	2099	2027	0	0
T3	336889	336814	0	0
T4	557141	557106	0	0
T5	938	845	0	0
T6	1360	1280	0	0
T7	15206	15147	0	0
T8	440701	440642	0	0
T9	249066	249060	0	0
T10	196026	195968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0