Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T11
1	0	Covered	T4,T9,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T11
1	0	Unreachable
1	1	Covered	T4,T9,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T9
1	0	Covered	T3,T4,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T3,T4,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T9
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	752754877	596215783	0	0
CheckNGreaterZero_A	2925	2925	0	0
GntImpliesReady_A	752754877	3887221	0	0
GntImpliesValid_A	752754877	3887221	0	0
GrantKnown_A	752754877	596215783	0	0
IdxKnown_A	752754877	596215783	0	0
IndexIsCorrect_A	752754877	3887221	0	0
LockArbDecision_A	752754877	0	0	0
NoReadyValidNoGrant_A	752754877	0	0	0
ReadyAndValidImplyGrant_A	752754877	3887221	0	0
ReqAndReadyImplyGrant_A	752754877	3887221	0	0
ReqImpliesValid_A	752754877	3887221	0	0
ReqStaysHighUntilGranted0_M	752754877	0	0	0
RoundRobin_A	752754877	5	0	975
ValidKnown_A	752754877	596215783	0	0
gen_data_port_assertion.DataFlow_A	752754877	3887221	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	752754877	596215783	0	0
T1	24420	24359	0	0
T2	2099	2027	0	0
T3	390860	390785	0	0
T4	2135611	1336954	0	0
T5	938	845	0	0
T6	1360	1280	0	0
T7	20522	17352	0	0
T8	549101	494842	0	0
T9	1450384	840821	0	0
T10	385138	290524	0	0
T11	518906	254573	0	0
T12	152158	71112	0	0
T13	24688	12344	0	0
T14	655967	647888	0	0
T15	0	78306	0	0
T24	101115	96656	0	0
T25	0	144	0	0
T26	0	81960	0	0
T27	0	89952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2925	2925	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	752754877	3887221	0	0
T1	20098	832	0	0
T2	2099	0	0	0
T3	390860	1580	0	0
T4	2135611	24676	0	0
T5	938	0	0	0
T6	1360	0	0	0
T7	20522	832	0	0
T8	549101	832	0	0
T9	1450384	18472	0	0
T10	385138	832	0	0
T11	518906	11134	0	0
T12	152158	0	0	0
T13	24688	0	0	0
T14	1311934	18800	0	0
T16	0	20410	0	0
T17	0	2282	0	0
T24	101115	6761	0	0
T26	0	3320	0	0
T35	0	6276	0	0
T36	0	8639	0	0
T43	0	532	0	0
T45	0	78	0	0
T46	0	118	0	0
T47	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	752754877	3887221	0	0
T1	20098	832	0	0
T2	2099	0	0	0
T3	390860	1580	0	0
T4	2135611	24676	0	0
T5	938	0	0	0
T6	1360	0	0	0
T7	20522	832	0	0
T8	549101	832	0	0
T9	1450384	18472	0	0
T10	385138	832	0	0
T11	518906	11134	0	0
T12	152158	0	0	0
T13	24688	0	0	0
T14	1311934	18800	0	0
T16	0	20410	0	0
T17	0	2282	0	0
T24	101115	6761	0	0
T26	0	3320	0	0
T35	0	6276	0	0
T36	0	8639	0	0
T43	0	532	0	0
T45	0	78	0	0
T46	0	118	0	0
T47	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	752754877	596215783	0	0
T1	24420	24359	0	0
T2	2099	2027	0	0
T3	390860	390785	0	0
T4	2135611	1336954	0	0
T5	938	845	0	0
T6	1360	1280	0	0
T7	20522	17352	0	0
T8	549101	494842	0	0
T9	1450384	840821	0	0
T10	385138	290524	0	0
T11	518906	254573	0	0
T12	152158	71112	0	0
T13	24688	12344	0	0
T14	655967	647888	0	0
T15	0	78306	0	0
T24	101115	96656	0	0
T25	0	144	0	0
T26	0	81960	0	0
T27	0	89952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	752754877	596215783	0	0
T1	24420	24359	0	0
T2	2099	2027	0	0
T3	390860	390785	0	0
T4	2135611	1336954	0	0
T5	938	845	0	0
T6	1360	1280	0	0
T7	20522	17352	0	0
T8	549101	494842	0	0
T9	1450384	840821	0	0
T10	385138	290524	0	0
T11	518906	254573	0	0
T12	152158	71112	0	0
T13	24688	12344	0	0
T14	655967	647888	0	0
T15	0	78306	0	0
T24	101115	96656	0	0
T25	0	144	0	0
T26	0	81960	0	0
T27	0	89952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	752754877	3887221	0	0
T1	20098	832	0	0
T2	2099	0	0	0
T3	390860	1580	0	0
T4	2135611	24676	0	0
T5	938	0	0	0
T6	1360	0	0	0
T7	20522	832	0	0
T8	549101	832	0	0
T9	1450384	18472	0	0
T10	385138	832	0	0
T11	518906	11134	0	0
T12	152158	0	0	0
T13	24688	0	0	0
T14	1311934	18800	0	0
T16	0	20410	0	0
T17	0	2282	0	0
T24	101115	6761	0	0
T26	0	3320	0	0
T35	0	6276	0	0
T36	0	8639	0	0
T43	0	532	0	0
T45	0	78	0	0
T46	0	118	0	0
T47	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	752754877	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	752754877	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	752754877	3887221	0	0
T1	20098	832	0	0
T2	2099	0	0	0
T3	390860	1580	0	0
T4	2135611	24676	0	0
T5	938	0	0	0
T6	1360	0	0	0
T7	20522	832	0	0
T8	549101	832	0	0
T9	1450384	18472	0	0
T10	385138	832	0	0
T11	518906	11134	0	0
T12	152158	0	0	0
T13	24688	0	0	0
T14	1311934	18800	0	0
T16	0	20410	0	0
T17	0	2282	0	0
T24	101115	6761	0	0
T26	0	3320	0	0
T35	0	6276	0	0
T36	0	8639	0	0
T43	0	532	0	0
T45	0	78	0	0
T46	0	118	0	0
T47	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	752754877	3887221	0	0
T1	20098	832	0	0
T2	2099	0	0	0
T3	390860	1580	0	0
T4	2135611	24676	0	0
T5	938	0	0	0
T6	1360	0	0	0
T7	20522	832	0	0
T8	549101	832	0	0
T9	1450384	18472	0	0
T10	385138	832	0	0
T11	518906	11134	0	0
T12	152158	0	0	0
T13	24688	0	0	0
T14	1311934	18800	0	0
T16	0	20410	0	0
T17	0	2282	0	0
T24	101115	6761	0	0
T26	0	3320	0	0
T35	0	6276	0	0
T36	0	8639	0	0
T43	0	532	0	0
T45	0	78	0	0
T46	0	118	0	0
T47	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	752754877	3887221	0	0
T1	20098	832	0	0
T2	2099	0	0	0
T3	390860	1580	0	0
T4	2135611	24676	0	0
T5	938	0	0	0
T6	1360	0	0	0
T7	20522	832	0	0
T8	549101	832	0	0
T9	1450384	18472	0	0
T10	385138	832	0	0
T11	518906	11134	0	0
T12	152158	0	0	0
T13	24688	0	0	0
T14	1311934	18800	0	0
T16	0	20410	0	0
T17	0	2282	0	0
T24	101115	6761	0	0
T26	0	3320	0	0
T35	0	6276	0	0
T36	0	8639	0	0
T43	0	532	0	0
T45	0	78	0	0
T46	0	118	0	0
T47	0	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	752754877	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	752754877	5	0	975
T48	262697	1	0	1
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	973182	0	0	1
T54	3540	0	0	1
T55	951	0	0	1
T56	84883	0	0	1
T57	144228	0	0	1
T58	904836	0	0	1
T59	801	0	0	1
T60	2322	0	0	1
T61	594501	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	752754877	596215783	0	0
T1	24420	24359	0	0
T2	2099	2027	0	0
T3	390860	390785	0	0
T4	2135611	1336954	0	0
T5	938	845	0	0
T6	1360	1280	0	0
T7	20522	17352	0	0
T8	549101	494842	0	0
T9	1450384	840821	0	0
T10	385138	290524	0	0
T11	518906	254573	0	0
T12	152158	71112	0	0
T13	24688	12344	0	0
T14	655967	647888	0	0
T15	0	78306	0	0
T24	101115	96656	0	0
T25	0	144	0	0
T26	0	81960	0	0
T27	0	89952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	752754877	3887221	0	0
T1	20098	832	0	0
T2	2099	0	0	0
T3	390860	1580	0	0
T4	2135611	24676	0	0
T5	938	0	0	0
T6	1360	0	0	0
T7	20522	832	0	0
T8	549101	832	0	0
T9	1450384	18472	0	0
T10	385138	832	0	0
T11	518906	11134	0	0
T12	152158	0	0	0
T13	24688	0	0	0
T14	1311934	18800	0	0
T16	0	20410	0	0
T17	0	2282	0	0
T24	101115	6761	0	0
T26	0	3320	0	0
T35	0	6276	0	0
T36	0	8639	0	0
T43	0	532	0	0
T45	0	78	0	0
T46	0	118	0	0
T47	0	14	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T11
1	0	Covered	T4,T9,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T11
1	0	Unreachable
1	1	Covered	T4,T9,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T9,T11
0	0	1	Unreachable
0	0	0	Covered	T4,T9,T11

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T9,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T9,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	154995479	33025378	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	154995479	719340	0	0
GntImpliesValid_A	154995479	719340	0	0
GrantKnown_A	154995479	33025378	0	0
IdxKnown_A	154995479	33025378	0	0
IndexIsCorrect_A	154995479	719340	0	0
LockArbDecision_A	154995479	0	0	0
NoReadyValidNoGrant_A	154995479	0	0	0
ReadyAndValidImplyGrant_A	154995479	719340	0	0
ReqAndReadyImplyGrant_A	154995479	719340	0	0
ReqImpliesValid_A	154995479	719340	0	0
ReqStaysHighUntilGranted0_M	154995479	0	0	0
RoundRobin_A	154995479	0	0	0
ValidKnown_A	154995479	33025378	0	0
gen_data_port_assertion.DataFlow_A	154995479	719340	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154995479	33025378	0	0
T4	789235	80528	0	0
T7	2658	0	0	0
T8	54200	0	0	0
T9	600659	54432	0	0
T10	94556	0	0	0
T11	259453	128328	0	0
T12	76079	71112	0	0
T13	12344	12344	0	0
T14	655967	166392	0	0
T24	101115	96656	0	0
T25	0	144	0	0
T26	0	81960	0	0
T27	0	89952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154995479	719340	0	0
T4	789235	3845	0	0
T7	2658	0	0	0
T8	54200	0	0	0
T9	600659	1768	0	0
T10	94556	0	0	0
T11	259453	5419	0	0
T12	76079	0	0	0
T13	12344	0	0	0
T14	655967	6855	0	0
T16	0	5957	0	0
T17	0	2282	0	0
T24	101115	4784	0	0
T26	0	3320	0	0
T45	0	78	0	0
T46	0	118	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154995479	719340	0	0
T4	789235	3845	0	0
T7	2658	0	0	0
T8	54200	0	0	0
T9	600659	1768	0	0
T10	94556	0	0	0
T11	259453	5419	0	0
T12	76079	0	0	0
T13	12344	0	0	0
T14	655967	6855	0	0
T16	0	5957	0	0
T17	0	2282	0	0
T24	101115	4784	0	0
T26	0	3320	0	0
T45	0	78	0	0
T46	0	118	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154995479	33025378	0	0
T4	789235	80528	0	0
T7	2658	0	0	0
T8	54200	0	0	0
T9	600659	54432	0	0
T10	94556	0	0	0
T11	259453	128328	0	0
T12	76079	71112	0	0
T13	12344	12344	0	0
T14	655967	166392	0	0
T24	101115	96656	0	0
T25	0	144	0	0
T26	0	81960	0	0
T27	0	89952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154995479	33025378	0	0
T4	789235	80528	0	0
T7	2658	0	0	0
T8	54200	0	0	0
T9	600659	54432	0	0
T10	94556	0	0	0
T11	259453	128328	0	0
T12	76079	71112	0	0
T13	12344	12344	0	0
T14	655967	166392	0	0
T24	101115	96656	0	0
T25	0	144	0	0
T26	0	81960	0	0
T27	0	89952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154995479	719340	0	0
T4	789235	3845	0	0
T7	2658	0	0	0
T8	54200	0	0	0
T9	600659	1768	0	0
T10	94556	0	0	0
T11	259453	5419	0	0
T12	76079	0	0	0
T13	12344	0	0	0
T14	655967	6855	0	0
T16	0	5957	0	0
T17	0	2282	0	0
T24	101115	4784	0	0
T26	0	3320	0	0
T45	0	78	0	0
T46	0	118	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154995479	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154995479	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154995479	719340	0	0
T4	789235	3845	0	0
T7	2658	0	0	0
T8	54200	0	0	0
T9	600659	1768	0	0
T10	94556	0	0	0
T11	259453	5419	0	0
T12	76079	0	0	0
T13	12344	0	0	0
T14	655967	6855	0	0
T16	0	5957	0	0
T17	0	2282	0	0
T24	101115	4784	0	0
T26	0	3320	0	0
T45	0	78	0	0
T46	0	118	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154995479	719340	0	0
T4	789235	3845	0	0
T7	2658	0	0	0
T8	54200	0	0	0
T9	600659	1768	0	0
T10	94556	0	0	0
T11	259453	5419	0	0
T12	76079	0	0	0
T13	12344	0	0	0
T14	655967	6855	0	0
T16	0	5957	0	0
T17	0	2282	0	0
T24	101115	4784	0	0
T26	0	3320	0	0
T45	0	78	0	0
T46	0	118	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154995479	719340	0	0
T4	789235	3845	0	0
T7	2658	0	0	0
T8	54200	0	0	0
T9	600659	1768	0	0
T10	94556	0	0	0
T11	259453	5419	0	0
T12	76079	0	0	0
T13	12344	0	0	0
T14	655967	6855	0	0
T16	0	5957	0	0
T17	0	2282	0	0
T24	101115	4784	0	0
T26	0	3320	0	0
T45	0	78	0	0
T46	0	118	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	154995479	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154995479	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154995479	33025378	0	0
T4	789235	80528	0	0
T7	2658	0	0	0
T8	54200	0	0	0
T9	600659	54432	0	0
T10	94556	0	0	0
T11	259453	128328	0	0
T12	76079	71112	0	0
T13	12344	12344	0	0
T14	655967	166392	0	0
T24	101115	96656	0	0
T25	0	144	0	0
T26	0	81960	0	0
T27	0	89952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154995479	719340	0	0
T4	789235	3845	0	0
T7	2658	0	0	0
T8	54200	0	0	0
T9	600659	1768	0	0
T10	94556	0	0	0
T11	259453	5419	0	0
T12	76079	0	0	0
T13	12344	0	0	0
T14	655967	6855	0	0
T16	0	5957	0	0
T17	0	2282	0	0
T24	101115	4784	0	0
T26	0	3320	0	0
T45	0	78	0	0
T46	0	118	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T9
1	0	Covered	T3,T4,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T3,T4,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T9
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	154995479	120514466	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	154995479	849553	0	0
GntImpliesValid_A	154995479	849553	0	0
GrantKnown_A	154995479	120514466	0	0
IdxKnown_A	154995479	120514466	0	0
IndexIsCorrect_A	154995479	849553	0	0
LockArbDecision_A	154995479	0	0	0
NoReadyValidNoGrant_A	154995479	0	0	0
ReadyAndValidImplyGrant_A	154995479	849553	0	0
ReqAndReadyImplyGrant_A	154995479	849553	0	0
ReqImpliesValid_A	154995479	849553	0	0
ReqStaysHighUntilGranted0_M	154995479	0	0	0
RoundRobin_A	154995479	0	0	0
ValidKnown_A	154995479	120514466	0	0
gen_data_port_assertion.DataFlow_A	154995479	849553	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154995479	120514466	0	0
T1	4322	4322	0	0
T3	53971	53971	0	0
T4	789235	699320	0	0
T7	2658	2205	0	0
T8	54200	54200	0	0
T9	600659	537329	0	0
T10	94556	94556	0	0
T11	259453	126245	0	0
T12	76079	0	0	0
T13	12344	0	0	0
T14	0	481496	0	0
T15	0	78306	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154995479	849553	0	0
T3	53971	646	0	0
T4	789235	7059	0	0
T7	2658	0	0	0
T8	54200	0	0	0
T9	600659	3709	0	0
T10	94556	0	0	0
T11	259453	1315	0	0
T12	76079	0	0	0
T13	12344	0	0	0
T14	655967	3716	0	0
T16	0	14453	0	0
T35	0	6276	0	0
T36	0	8639	0	0
T43	0	532	0	0
T47	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154995479	849553	0	0
T3	53971	646	0	0
T4	789235	7059	0	0
T7	2658	0	0	0
T8	54200	0	0	0
T9	600659	3709	0	0
T10	94556	0	0	0
T11	259453	1315	0	0
T12	76079	0	0	0
T13	12344	0	0	0
T14	655967	3716	0	0
T16	0	14453	0	0
T35	0	6276	0	0
T36	0	8639	0	0
T43	0	532	0	0
T47	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154995479	120514466	0	0
T1	4322	4322	0	0
T3	53971	53971	0	0
T4	789235	699320	0	0
T7	2658	2205	0	0
T8	54200	54200	0	0
T9	600659	537329	0	0
T10	94556	94556	0	0
T11	259453	126245	0	0
T12	76079	0	0	0
T13	12344	0	0	0
T14	0	481496	0	0
T15	0	78306	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154995479	120514466	0	0
T1	4322	4322	0	0
T3	53971	53971	0	0
T4	789235	699320	0	0
T7	2658	2205	0	0
T8	54200	54200	0	0
T9	600659	537329	0	0
T10	94556	94556	0	0
T11	259453	126245	0	0
T12	76079	0	0	0
T13	12344	0	0	0
T14	0	481496	0	0
T15	0	78306	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154995479	849553	0	0
T3	53971	646	0	0
T4	789235	7059	0	0
T7	2658	0	0	0
T8	54200	0	0	0
T9	600659	3709	0	0
T10	94556	0	0	0
T11	259453	1315	0	0
T12	76079	0	0	0
T13	12344	0	0	0
T14	655967	3716	0	0
T16	0	14453	0	0
T35	0	6276	0	0
T36	0	8639	0	0
T43	0	532	0	0
T47	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154995479	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154995479	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154995479	849553	0	0
T3	53971	646	0	0
T4	789235	7059	0	0
T7	2658	0	0	0
T8	54200	0	0	0
T9	600659	3709	0	0
T10	94556	0	0	0
T11	259453	1315	0	0
T12	76079	0	0	0
T13	12344	0	0	0
T14	655967	3716	0	0
T16	0	14453	0	0
T35	0	6276	0	0
T36	0	8639	0	0
T43	0	532	0	0
T47	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154995479	849553	0	0
T3	53971	646	0	0
T4	789235	7059	0	0
T7	2658	0	0	0
T8	54200	0	0	0
T9	600659	3709	0	0
T10	94556	0	0	0
T11	259453	1315	0	0
T12	76079	0	0	0
T13	12344	0	0	0
T14	655967	3716	0	0
T16	0	14453	0	0
T35	0	6276	0	0
T36	0	8639	0	0
T43	0	532	0	0
T47	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154995479	849553	0	0
T3	53971	646	0	0
T4	789235	7059	0	0
T7	2658	0	0	0
T8	54200	0	0	0
T9	600659	3709	0	0
T10	94556	0	0	0
T11	259453	1315	0	0
T12	76079	0	0	0
T13	12344	0	0	0
T14	655967	3716	0	0
T16	0	14453	0	0
T35	0	6276	0	0
T36	0	8639	0	0
T43	0	532	0	0
T47	0	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	154995479	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154995479	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154995479	120514466	0	0
T1	4322	4322	0	0
T3	53971	53971	0	0
T4	789235	699320	0	0
T7	2658	2205	0	0
T8	54200	54200	0	0
T9	600659	537329	0	0
T10	94556	94556	0	0
T11	259453	126245	0	0
T12	76079	0	0	0
T13	12344	0	0	0
T14	0	481496	0	0
T15	0	78306	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154995479	849553	0	0
T3	53971	646	0	0
T4	789235	7059	0	0
T7	2658	0	0	0
T8	54200	0	0	0
T9	600659	3709	0	0
T10	94556	0	0	0
T11	259453	1315	0	0
T12	76079	0	0	0
T13	12344	0	0	0
T14	655967	3716	0	0
T16	0	14453	0	0
T35	0	6276	0	0
T36	0	8639	0	0
T43	0	532	0	0
T47	0	14	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T9
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442763919	442675939	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	442763919	2318328	0	0
GntImpliesValid_A	442763919	2318328	0	0
GrantKnown_A	442763919	442675939	0	0
IdxKnown_A	442763919	442675939	0	0
IndexIsCorrect_A	442763919	2318328	0	0
LockArbDecision_A	442763919	0	0	0
NoReadyValidNoGrant_A	442763919	0	0	0
ReadyAndValidImplyGrant_A	442763919	2318328	0	0
ReqAndReadyImplyGrant_A	442763919	2318328	0	0
ReqImpliesValid_A	442763919	2318328	0	0
ReqStaysHighUntilGranted0_M	442763919	0	0	0
RoundRobin_A	442763919	5	0	975
ValidKnown_A	442763919	442675939	0	0
gen_data_port_assertion.DataFlow_A	442763919	2318328	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442763919	442675939	0	0
T1	20098	20037	0	0
T2	2099	2027	0	0
T3	336889	336814	0	0
T4	557141	557106	0	0
T5	938	845	0	0
T6	1360	1280	0	0
T7	15206	15147	0	0
T8	440701	440642	0	0
T9	249066	249060	0	0
T10	196026	195968	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442763919	2318328	0	0
T1	20098	832	0	0
T2	2099	0	0	0
T3	336889	934	0	0
T4	557141	13772	0	0
T5	938	0	0	0
T6	1360	0	0	0
T7	15206	832	0	0
T8	440701	832	0	0
T9	249066	12995	0	0
T10	196026	832	0	0
T11	0	4400	0	0
T14	0	8229	0	0
T24	0	1977	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442763919	2318328	0	0
T1	20098	832	0	0
T2	2099	0	0	0
T3	336889	934	0	0
T4	557141	13772	0	0
T5	938	0	0	0
T6	1360	0	0	0
T7	15206	832	0	0
T8	440701	832	0	0
T9	249066	12995	0	0
T10	196026	832	0	0
T11	0	4400	0	0
T14	0	8229	0	0
T24	0	1977	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442763919	442675939	0	0
T1	20098	20037	0	0
T2	2099	2027	0	0
T3	336889	336814	0	0
T4	557141	557106	0	0
T5	938	845	0	0
T6	1360	1280	0	0
T7	15206	15147	0	0
T8	440701	440642	0	0
T9	249066	249060	0	0
T10	196026	195968	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442763919	442675939	0	0
T1	20098	20037	0	0
T2	2099	2027	0	0
T3	336889	336814	0	0
T4	557141	557106	0	0
T5	938	845	0	0
T6	1360	1280	0	0
T7	15206	15147	0	0
T8	440701	440642	0	0
T9	249066	249060	0	0
T10	196026	195968	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442763919	2318328	0	0
T1	20098	832	0	0
T2	2099	0	0	0
T3	336889	934	0	0
T4	557141	13772	0	0
T5	938	0	0	0
T6	1360	0	0	0
T7	15206	832	0	0
T8	440701	832	0	0
T9	249066	12995	0	0
T10	196026	832	0	0
T11	0	4400	0	0
T14	0	8229	0	0
T24	0	1977	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442763919	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442763919	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442763919	2318328	0	0
T1	20098	832	0	0
T2	2099	0	0	0
T3	336889	934	0	0
T4	557141	13772	0	0
T5	938	0	0	0
T6	1360	0	0	0
T7	15206	832	0	0
T8	440701	832	0	0
T9	249066	12995	0	0
T10	196026	832	0	0
T11	0	4400	0	0
T14	0	8229	0	0
T24	0	1977	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442763919	2318328	0	0
T1	20098	832	0	0
T2	2099	0	0	0
T3	336889	934	0	0
T4	557141	13772	0	0
T5	938	0	0	0
T6	1360	0	0	0
T7	15206	832	0	0
T8	440701	832	0	0
T9	249066	12995	0	0
T10	196026	832	0	0
T11	0	4400	0	0
T14	0	8229	0	0
T24	0	1977	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442763919	2318328	0	0
T1	20098	832	0	0
T2	2099	0	0	0
T3	336889	934	0	0
T4	557141	13772	0	0
T5	938	0	0	0
T6	1360	0	0	0
T7	15206	832	0	0
T8	440701	832	0	0
T9	249066	12995	0	0
T10	196026	832	0	0
T11	0	4400	0	0
T14	0	8229	0	0
T24	0	1977	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442763919	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442763919	5	0	975
T48	262697	1	0	1
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	973182	0	0	1
T54	3540	0	0	1
T55	951	0	0	1
T56	84883	0	0	1
T57	144228	0	0	1
T58	904836	0	0	1
T59	801	0	0	1
T60	2322	0	0	1
T61	594501	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442763919	442675939	0	0
T1	20098	20037	0	0
T2	2099	2027	0	0
T3	336889	336814	0	0
T4	557141	557106	0	0
T5	938	845	0	0
T6	1360	1280	0	0
T7	15206	15147	0	0
T8	440701	440642	0	0
T9	249066	249060	0	0
T10	196026	195968	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442763919	2318328	0	0
T1	20098	832	0	0
T2	2099	0	0	0
T3	336889	934	0	0
T4	557141	13772	0	0
T5	938	0	0	0
T6	1360	0	0	0
T7	15206	832	0	0
T8	440701	832	0	0
T9	249066	12995	0	0
T10	196026	832	0	0
T11	0	4400	0	0
T14	0	8229	0	0
T24	0	1977	0	0