Unified Coverage Report :: Module :: spi_device_csr_assert_fpv

Module : spi_device_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_spi_device_csr_assert_0/spi_device_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.spi_device_csr_assert	100.00						100.00

---

Module Instance : tb.dut.spi_device_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : spi_device_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	58	58	100.00	58	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	58	58	100.00	58	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	445284861	3845	0	0
addr_swap_data_rd_A	445284861	2520	0	0
addr_swap_mask_rd_A	445284861	2666	0	0
cfg_rd_A	445284861	3019	0	0
cmd_filter_0_rd_A	445284861	8525	0	0
cmd_filter_1_rd_A	445284861	8116	0	0
cmd_filter_2_rd_A	445284861	8393	0	0
cmd_filter_3_rd_A	445284861	8515	0	0
cmd_filter_4_rd_A	445284861	8594	0	0
cmd_filter_5_rd_A	445284861	9141	0	0
cmd_filter_6_rd_A	445284861	8099	0	0
cmd_filter_7_rd_A	445284861	8419	0	0
cmd_info_0_rd_A	445284861	4896	0	0
cmd_info_10_rd_A	445284861	4741	0	0
cmd_info_11_rd_A	445284861	5274	0	0
cmd_info_12_rd_A	445284861	4985	0	0
cmd_info_13_rd_A	445284861	5211	0	0
cmd_info_14_rd_A	445284861	5114	0	0
cmd_info_15_rd_A	445284861	4536	0	0
cmd_info_16_rd_A	445284861	4647	0	0
cmd_info_17_rd_A	445284861	5179	0	0
cmd_info_18_rd_A	445284861	5256	0	0
cmd_info_19_rd_A	445284861	4700	0	0
cmd_info_1_rd_A	445284861	4782	0	0
cmd_info_20_rd_A	445284861	4770	0	0
cmd_info_21_rd_A	445284861	5158	0	0
cmd_info_22_rd_A	445284861	4904	0	0
cmd_info_23_rd_A	445284861	5031	0	0
cmd_info_2_rd_A	445284861	4767	0	0
cmd_info_3_rd_A	445284861	4838	0	0
cmd_info_4_rd_A	445284861	5040	0	0
cmd_info_5_rd_A	445284861	4846	0	0
cmd_info_6_rd_A	445284861	5038	0	0
cmd_info_7_rd_A	445284861	5034	0	0
cmd_info_8_rd_A	445284861	5181	0	0
cmd_info_9_rd_A	445284861	4937	0	0
cmd_info_en4b_rd_A	445284861	2808	0	0
cmd_info_ex4b_rd_A	445284861	2979	0	0
cmd_info_wrdi_rd_A	445284861	3001	0	0
cmd_info_wren_rd_A	445284861	2803	0	0
intercept_en_rd_A	445284861	3281	0	0
intr_enable_rd_A	445284861	4945	0	0
jedec_cc_rd_A	445284861	2728	0	0
jedec_id_rd_A	445284861	2966	0	0
mailbox_addr_rd_A	445284861	2566	0	0
payload_swap_data_rd_A	445284861	2581	0	0
payload_swap_mask_rd_A	445284861	2555	0	0
read_threshold_rd_A	445284861	2696	0	0
tpm_access_0_rd_A	445284861	3253	0	0
tpm_access_1_rd_A	445284861	2679	0	0
tpm_cfg_rd_A	445284861	3476	0	0
tpm_did_vid_rd_A	445284861	2670	0	0
tpm_int_enable_rd_A	445284861	2468	0	0
tpm_int_status_rd_A	445284861	2529	0	0
tpm_int_vector_rd_A	445284861	2619	0	0
tpm_intf_capability_rd_A	445284861	2506	0	0
tpm_rid_rd_A	445284861	2618	0	0
tpm_sts_rd_A	445284861	2534	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	3845	0	0
T89	10604	185	0	0
T90	9451	10	0	0
T92	5127	4	0	0
T93	27341	2	0	0
T94	11685	8	0	0
T95	97069	4	0	0
T97	10595	125	0	0
T112	8149	3	0	0
T114	14930	13	0	0
T117	8420	2	0	0

addr_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	2520	0	0
T76	1815	2	0	0
T95	97069	94	0	0
T114	14930	11	0	0
T118	9525	1	0	0
T124	180125	451	0	0
T127	11007	16	0	0
T139	7694	28	0	0
T154	6097	1	0	0
T155	7042	6	0	0
T156	14502	18	0	0

addr_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	2666	0	0
T76	1815	6	0	0
T95	97069	124	0	0
T114	14930	18	0	0
T118	9525	14	0	0
T124	180125	375	0	0
T127	11007	16	0	0
T139	7694	17	0	0
T154	6097	7	0	0
T155	7042	16	0	0
T156	14502	37	0	0

cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	3019	0	0
T95	97069	233	0	0
T114	14930	17	0	0
T118	9525	16	0	0
T124	180125	466	0	0
T127	11007	26	0	0
T139	7694	17	0	0
T154	6097	16	0	0
T155	7042	6	0	0
T156	14502	32	0	0
T157	30653	50	0	0

cmd_filter_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	8525	0	0
T76	1815	2	0	0
T95	97069	1544	0	0
T114	14930	251	0	0
T118	9525	97	0	0
T124	180125	386	0	0
T127	11007	338	0	0
T139	7694	48	0	0
T154	6097	116	0	0
T155	7042	51	0	0
T156	14502	28	0	0

cmd_filter_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	8116	0	0
T76	1815	9	0	0
T95	97069	1633	0	0
T114	14930	223	0	0
T118	9525	70	0	0
T124	180125	485	0	0
T127	11007	242	0	0
T139	7694	34	0	0
T154	6097	104	0	0
T155	7042	38	0	0
T156	14502	45	0	0

cmd_filter_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	8393	0	0
T76	1815	3	0	0
T95	97069	1586	0	0
T114	14930	48	0	0
T118	9525	4	0	0
T124	180125	461	0	0
T127	11007	138	0	0
T139	7694	39	0	0
T154	6097	8	0	0
T155	7042	35	0	0
T156	14502	21	0	0

cmd_filter_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	8515	0	0
T76	1815	3	0	0
T95	97069	1399	0	0
T114	14930	93	0	0
T118	9525	8	0	0
T124	180125	443	0	0
T127	11007	131	0	0
T139	7694	39	0	0
T154	6097	8	0	0
T155	7042	46	0	0
T156	14502	61	0	0

cmd_filter_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	8594	0	0
T76	1815	9	0	0
T95	97069	1779	0	0
T114	14930	11	0	0
T118	9525	180	0	0
T124	180125	449	0	0
T127	11007	142	0	0
T139	7694	18	0	0
T154	6097	131	0	0
T155	7042	27	0	0
T156	14502	16	0	0

cmd_filter_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	9141	0	0
T76	1815	1	0	0
T95	97069	2211	0	0
T114	14930	207	0	0
T118	9525	73	0	0
T124	180125	433	0	0
T127	11007	114	0	0
T139	7694	13	0	0
T154	6097	15	0	0
T155	7042	6	0	0
T156	14502	64	0	0

cmd_filter_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	8099	0	0
T76	1815	4	0	0
T95	97069	1300	0	0
T114	14930	125	0	0
T118	9525	6	0	0
T124	180125	445	0	0
T127	11007	266	0	0
T139	7694	36	0	0
T154	6097	144	0	0
T155	7042	26	0	0
T156	14502	85	0	0

cmd_filter_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	8419	0	0
T76	1815	5	0	0
T95	97069	2018	0	0
T114	14930	87	0	0
T118	9525	57	0	0
T124	180125	411	0	0
T127	11007	215	0	0
T139	7694	9	0	0
T154	6097	128	0	0
T155	7042	20	0	0
T156	14502	9	0	0

cmd_info_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	4896	0	0
T76	1815	6	0	0
T95	97069	794	0	0
T114	14930	38	0	0
T118	9525	4	0	0
T124	180125	388	0	0
T127	11007	96	0	0
T139	7694	25	0	0
T154	6097	3	0	0
T155	7042	30	0	0
T156	14502	35	0	0

cmd_info_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	4741	0	0
T76	1815	5	0	0
T95	97069	613	0	0
T114	14930	51	0	0
T118	9525	38	0	0
T124	180125	452	0	0
T127	11007	18	0	0
T139	7694	37	0	0
T154	6097	17	0	0
T155	7042	33	0	0
T156	14502	5	0	0

cmd_info_11_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	5274	0	0
T95	97069	875	0	0
T114	14930	82	0	0
T118	9525	42	0	0
T124	180125	480	0	0
T127	11007	49	0	0
T139	7694	23	0	0
T154	6097	5	0	0
T155	7042	43	0	0
T156	14502	36	0	0
T157	30653	215	0	0

cmd_info_12_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	4985	0	0
T76	1815	3	0	0
T95	97069	767	0	0
T114	14930	51	0	0
T118	9525	1	0	0
T124	180125	408	0	0
T127	11007	150	0	0
T139	7694	11	0	0
T154	6097	66	0	0
T155	7042	13	0	0
T156	14502	28	0	0

cmd_info_13_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	5211	0	0
T76	1815	5	0	0
T95	97069	889	0	0
T114	14930	81	0	0
T118	9525	54	0	0
T124	180125	476	0	0
T127	11007	42	0	0
T139	7694	24	0	0
T154	6097	2	0	0
T155	7042	6	0	0
T156	14502	20	0	0

cmd_info_14_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	5114	0	0
T95	97069	853	0	0
T114	14930	54	0	0
T118	9525	18	0	0
T124	180125	431	0	0
T127	11007	96	0	0
T139	7694	1	0	0
T154	6097	8	0	0
T155	7042	17	0	0
T156	14502	62	0	0
T157	30653	110	0	0

cmd_info_15_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	4536	0	0
T76	1815	1	0	0
T95	97069	901	0	0
T114	14930	38	0	0
T118	9525	16	0	0
T124	180125	459	0	0
T127	11007	43	0	0
T154	6097	55	0	0
T155	7042	11	0	0
T156	14502	9	0	0
T157	30653	116	0	0

cmd_info_16_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	4647	0	0
T76	1815	1	0	0
T95	97069	497	0	0
T114	14930	49	0	0
T118	9525	45	0	0
T124	180125	473	0	0
T127	11007	106	0	0
T139	7694	15	0	0
T154	6097	62	0	0
T155	7042	20	0	0
T156	14502	14	0	0

cmd_info_17_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	5179	0	0
T76	1815	1	0	0
T95	97069	1165	0	0
T114	14930	56	0	0
T118	9525	37	0	0
T124	180125	464	0	0
T127	11007	60	0	0
T139	7694	8	0	0
T154	6097	7	0	0
T155	7042	27	0	0
T156	14502	6	0	0

cmd_info_18_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	5256	0	0
T76	1815	4	0	0
T95	97069	930	0	0
T114	14930	22	0	0
T118	9525	38	0	0
T124	180125	491	0	0
T127	11007	141	0	0
T139	7694	23	0	0
T154	6097	6	0	0
T155	7042	11	0	0
T156	14502	8	0	0

cmd_info_19_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	4700	0	0
T76	1815	3	0	0
T95	97069	1048	0	0
T114	14930	79	0	0
T118	9525	15	0	0
T124	180125	482	0	0
T127	11007	62	0	0
T139	7694	34	0	0
T154	6097	4	0	0
T155	7042	8	0	0
T156	14502	62	0	0

cmd_info_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	4782	0	0
T76	1815	2	0	0
T95	97069	823	0	0
T114	14930	91	0	0
T118	9525	33	0	0
T124	180125	418	0	0
T127	11007	107	0	0
T139	7694	24	0	0
T154	6097	13	0	0
T155	7042	9	0	0
T156	14502	48	0	0

cmd_info_20_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	4770	0	0
T76	1815	4	0	0
T95	97069	772	0	0
T114	14930	38	0	0
T118	9525	45	0	0
T124	180125	436	0	0
T127	11007	66	0	0
T139	7694	6	0	0
T154	6097	88	0	0
T155	7042	25	0	0
T156	14502	17	0	0

cmd_info_21_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	5158	0	0
T76	1815	6	0	0
T95	97069	858	0	0
T114	14930	38	0	0
T118	9525	11	0	0
T124	180125	469	0	0
T127	11007	102	0	0
T139	7694	30	0	0
T154	6097	65	0	0
T155	7042	62	0	0
T156	14502	50	0	0

cmd_info_22_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	4904	0	0
T76	1815	4	0	0
T95	97069	760	0	0
T114	14930	56	0	0
T118	9525	27	0	0
T124	180125	424	0	0
T127	11007	49	0	0
T139	7694	7	0	0
T154	6097	47	0	0
T155	7042	14	0	0
T156	14502	40	0	0

cmd_info_23_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	5031	0	0
T76	1815	3	0	0
T95	97069	808	0	0
T114	14930	28	0	0
T118	9525	44	0	0
T124	180125	451	0	0
T127	11007	99	0	0
T139	7694	7	0	0
T154	6097	59	0	0
T155	7042	10	0	0
T156	14502	32	0	0

cmd_info_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	4767	0	0
T76	1815	4	0	0
T95	97069	681	0	0
T114	14930	47	0	0
T118	9525	28	0	0
T124	180125	510	0	0
T127	11007	75	0	0
T139	7694	15	0	0
T154	6097	4	0	0
T155	7042	11	0	0
T156	14502	19	0	0

cmd_info_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	4838	0	0
T76	1815	7	0	0
T95	97069	664	0	0
T114	14930	98	0	0
T118	9525	51	0	0
T124	180125	454	0	0
T127	11007	98	0	0
T139	7694	19	0	0
T154	6097	69	0	0
T155	7042	18	0	0
T156	14502	71	0	0

cmd_info_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	5040	0	0
T76	1815	2	0	0
T95	97069	867	0	0
T114	14930	20	0	0
T118	9525	26	0	0
T124	180125	474	0	0
T127	11007	42	0	0
T139	7694	6	0	0
T154	6097	51	0	0
T156	14502	32	0	0
T157	30653	111	0	0

cmd_info_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	4846	0	0
T76	1815	2	0	0
T95	97069	698	0	0
T114	14930	24	0	0
T118	9525	3	0	0
T124	180125	437	0	0
T127	11007	54	0	0
T139	7694	44	0	0
T154	6097	56	0	0
T155	7042	7	0	0
T156	14502	26	0	0

cmd_info_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	5038	0	0
T76	1815	8	0	0
T95	97069	997	0	0
T114	14930	30	0	0
T118	9525	6	0	0
T124	180125	438	0	0
T127	11007	120	0	0
T139	7694	12	0	0
T154	6097	90	0	0
T155	7042	34	0	0
T156	14502	58	0	0

cmd_info_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	5034	0	0
T76	1815	3	0	0
T95	97069	748	0	0
T114	14930	57	0	0
T118	9525	17	0	0
T124	180125	456	0	0
T127	11007	150	0	0
T139	7694	26	0	0
T154	6097	5	0	0
T155	7042	41	0	0
T156	14502	61	0	0

cmd_info_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	5181	0	0
T76	1815	7	0	0
T95	97069	1035	0	0
T114	14930	30	0	0
T118	9525	7	0	0
T124	180125	519	0	0
T127	11007	12	0	0
T154	6097	8	0	0
T155	7042	10	0	0
T156	14502	43	0	0
T157	30653	200	0	0

cmd_info_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	4937	0	0
T76	1815	3	0	0
T95	97069	682	0	0
T114	14930	81	0	0
T118	9525	62	0	0
T124	180125	464	0	0
T127	11007	164	0	0
T139	7694	11	0	0
T154	6097	61	0	0
T155	7042	24	0	0
T156	14502	12	0	0

cmd_info_en4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	2808	0	0
T76	1815	4	0	0
T95	97069	222	0	0
T114	14930	33	0	0
T124	180125	479	0	0
T127	11007	21	0	0
T139	7694	8	0	0
T154	6097	12	0	0
T155	7042	16	0	0
T156	14502	28	0	0
T157	30653	29	0	0

cmd_info_ex4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	2979	0	0
T76	1815	4	0	0
T95	97069	202	0	0
T114	14930	12	0	0
T118	9525	8	0	0
T124	180125	442	0	0
T127	11007	17	0	0
T139	7694	10	0	0
T154	6097	13	0	0
T155	7042	26	0	0
T156	14502	26	0	0

cmd_info_wrdi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	3001	0	0
T76	1815	7	0	0
T95	97069	150	0	0
T114	14930	16	0	0
T118	9525	3	0	0
T124	180125	448	0	0
T127	11007	17	0	0
T139	7694	24	0	0
T154	6097	2	0	0
T155	7042	40	0	0
T156	14502	86	0	0

cmd_info_wren_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	2803	0	0
T76	1815	8	0	0
T95	97069	178	0	0
T114	14930	18	0	0
T118	9525	5	0	0
T124	180125	436	0	0
T127	11007	17	0	0
T139	7694	27	0	0
T154	6097	12	0	0
T155	7042	21	0	0
T156	14502	29	0	0

intercept_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	3281	0	0
T95	97069	212	0	0
T114	14930	11	0	0
T118	9525	23	0	0
T124	180125	435	0	0
T127	11007	20	0	0
T139	7694	28	0	0
T154	6097	24	0	0
T155	7042	30	0	0
T156	14502	101	0	0
T157	30653	47	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	4945	0	0
T14	268772	23	0	0
T15	552245	0	0	0
T20	0	7	0	0
T21	0	73	0	0
T22	0	17	0	0
T24	598213	0	0	0
T25	1322	0	0	0
T26	390036	0	0	0
T27	62537	0	0	0
T28	71977	0	0	0
T35	361578	0	0	0
T42	16432	0	0	0
T48	0	8	0	0
T51	0	17	0	0
T62	1111	0	0	0
T158	0	28	0	0
T159	0	7	0	0
T160	0	42	0	0
T161	0	40	0	0

jedec_cc_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	2728	0	0
T76	1815	4	0	0
T95	97069	141	0	0
T114	14930	3	0	0
T118	9525	12	0	0
T124	180125	476	0	0
T127	11007	12	0	0
T139	7694	29	0	0
T154	6097	8	0	0
T155	7042	6	0	0
T156	14502	48	0	0

jedec_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	2966	0	0
T76	1815	4	0	0
T95	97069	193	0	0
T114	14930	27	0	0
T118	9525	11	0	0
T124	180125	443	0	0
T127	11007	6	0	0
T139	7694	15	0	0
T154	6097	16	0	0
T155	7042	30	0	0
T156	14502	16	0	0

mailbox_addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	2566	0	0
T76	1815	1	0	0
T95	97069	108	0	0
T114	14930	14	0	0
T124	180125	461	0	0
T127	11007	8	0	0
T139	7694	27	0	0
T154	6097	10	0	0
T155	7042	26	0	0
T156	14502	24	0	0
T157	30653	13	0	0

payload_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	2581	0	0
T76	1815	2	0	0
T95	97069	120	0	0
T114	14930	6	0	0
T118	9525	15	0	0
T124	180125	450	0	0
T127	11007	14	0	0
T139	7694	8	0	0
T154	6097	6	0	0
T155	7042	17	0	0
T156	14502	71	0	0

payload_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	2555	0	0
T76	1815	7	0	0
T95	97069	101	0	0
T118	9525	7	0	0
T124	180125	434	0	0
T127	11007	23	0	0
T139	7694	18	0	0
T154	6097	13	0	0
T155	7042	28	0	0
T156	14502	91	0	0
T157	30653	17	0	0

read_threshold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	2696	0	0
T95	97069	131	0	0
T114	14930	17	0	0
T118	9525	13	0	0
T124	180125	485	0	0
T127	11007	8	0	0
T139	7694	27	0	0
T154	6097	9	0	0
T155	7042	36	0	0
T156	14502	33	0	0
T157	30653	33	0	0

tpm_access_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	3253	0	0
T76	1815	2	0	0
T95	97069	301	0	0
T114	14930	46	0	0
T118	9525	36	0	0
T124	180125	400	0	0
T127	11007	27	0	0
T139	7694	68	0	0
T154	6097	18	0	0
T155	7042	16	0	0
T156	14502	26	0	0

tpm_access_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	2679	0	0
T76	1815	4	0	0
T95	97069	103	0	0
T114	14930	14	0	0
T118	9525	4	0	0
T124	180125	467	0	0
T127	11007	16	0	0
T139	7694	3	0	0
T154	6097	17	0	0
T155	7042	37	0	0
T156	14502	68	0	0

tpm_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	3476	0	0
T76	1815	3	0	0
T95	97069	356	0	0
T114	14930	28	0	0
T118	9525	24	0	0
T124	180125	454	0	0
T127	11007	30	0	0
T139	7694	15	0	0
T154	6097	34	0	0
T155	7042	28	0	0
T156	14502	2	0	0

tpm_did_vid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	2670	0	0
T95	97069	180	0	0
T114	14930	19	0	0
T118	9525	8	0	0
T124	180125	368	0	0
T127	11007	10	0	0
T139	7694	10	0	0
T154	6097	9	0	0
T155	7042	3	0	0
T156	14502	32	0	0
T157	30653	25	0	0

tpm_int_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	2468	0	0
T76	1815	6	0	0
T95	97069	142	0	0
T114	14930	14	0	0
T118	9525	28	0	0
T124	180125	393	0	0
T127	11007	4	0	0
T139	7694	21	0	0
T154	6097	14	0	0
T155	7042	8	0	0
T156	14502	11	0	0

tpm_int_status_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	2529	0	0
T76	1815	7	0	0
T95	97069	117	0	0
T114	14930	16	0	0
T118	9525	12	0	0
T124	180125	436	0	0
T127	11007	7	0	0
T139	7694	3	0	0
T154	6097	19	0	0
T155	7042	1	0	0
T156	14502	40	0	0

tpm_int_vector_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	2619	0	0
T76	1815	5	0	0
T95	97069	114	0	0
T114	14930	4	0	0
T118	9525	6	0	0
T124	180125	440	0	0
T127	11007	8	0	0
T139	7694	20	0	0
T154	6097	8	0	0
T155	7042	30	0	0
T156	14502	25	0	0

tpm_intf_capability_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	2506	0	0
T95	97069	109	0	0
T114	14930	11	0	0
T118	9525	11	0	0
T124	180125	431	0	0
T127	11007	3	0	0
T139	7694	37	0	0
T154	6097	6	0	0
T155	7042	22	0	0
T156	14502	51	0	0
T157	30653	15	0	0

tpm_rid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	2618	0	0
T76	1815	1	0	0
T95	97069	94	0	0
T114	14930	26	0	0
T118	9525	16	0	0
T124	180125	541	0	0
T127	11007	10	0	0
T139	7694	3	0	0
T154	6097	12	0	0
T155	7042	20	0	0
T156	14502	50	0	0

tpm_sts_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445284861	2534	0	0
T76	1815	5	0	0
T95	97069	111	0	0
T114	14930	21	0	0
T118	9525	7	0	0
T124	180125	407	0	0
T127	11007	14	0	0
T139	7694	18	0	0
T154	6097	8	0	0
T155	7042	2	0	0
T156	14502	30	0	0