Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3333450	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4212898

1

T1

6095

T2

978

T3

24441

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4080833	1			T1	1540		T2	189		T3	21676
values[0x0]	1732734	1			T1	2714		T2	455		T3	12190
values[0x1]	1732781	1			T1	2570		T2	427		T3	12048

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2376441	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5169907

1

T1

6266

T2

987

T3

30732

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26183	1			T1	25		T3	179		T4	6
valid_sources[0x01]	28377	1			T1	10		T3	193		T4	4
valid_sources[0x02]	30515	1			T1	32		T3	177		T4	7
valid_sources[0x03]	28912	1			T1	14		T3	184		T4	3
valid_sources[0x04]	28050	1			T1	27		T3	153		T4	5
valid_sources[0x05]	27237	1			T1	30		T3	210		T4	2
valid_sources[0x06]	29322	1			T1	20		T3	201		T4	3
valid_sources[0x07]	28536	1			T1	25		T3	190		T4	4
valid_sources[0x08]	29837	1			T1	23		T3	193		T4	6
valid_sources[0x09]	25942	1			T1	15		T3	189		T4	6
valid_sources[0x0a]	27816	1			T1	23		T3	181		T4	5
valid_sources[0x0b]	31460	1			T1	27		T3	170		T4	2
valid_sources[0x0c]	28571	1			T1	13		T3	209		T4	5
valid_sources[0x0d]	28798	1			T1	27		T3	183		T4	3
valid_sources[0x0e]	28116	1			T1	24		T3	164		T4	7
valid_sources[0x0f]	28674	1			T1	20		T3	164		T4	2
valid_sources[0x10]	29840	1			T1	23		T3	179		T4	2
valid_sources[0x11]	26737	1			T1	55		T3	197		T4	3
valid_sources[0x12]	28333	1			T1	32		T3	179		T4	7
valid_sources[0x13]	29756	1			T1	36		T3	186		T4	5
valid_sources[0x14]	28995	1			T1	34		T3	167		T4	5
valid_sources[0x15]	27739	1			T1	30		T3	155		T4	5
valid_sources[0x16]	29411	1			T1	23		T3	185		T4	6
valid_sources[0x17]	26929	1			T1	36		T3	177		T4	5
valid_sources[0x18]	26790	1			T1	24		T3	179		T4	2
valid_sources[0x19]	43525	1			T1	51		T3	167		T4	5
valid_sources[0x1a]	28961	1			T1	20		T3	186		T4	3
valid_sources[0x1b]	26422	1			T1	42		T3	155		T4	2
valid_sources[0x1c]	26254	1			T1	17		T3	160		T4	3
valid_sources[0x1d]	33839	1			T1	50		T3	170		T4	5
valid_sources[0x1e]	27852	1			T1	11		T3	162		T4	3
valid_sources[0x1f]	31299	1			T1	21		T3	179		T4	3
valid_sources[0x20]	30360	1			T1	34		T3	181		T4	6
valid_sources[0x21]	30283	1			T1	37		T3	204		T4	3
valid_sources[0x22]	26297	1			T1	24		T3	176		T4	4
valid_sources[0x23]	27083	1			T1	29		T3	184		T4	3
valid_sources[0x24]	26899	1			T1	37		T3	188		T4	7
valid_sources[0x25]	28365	1			T1	35		T3	163		T4	4
valid_sources[0x26]	25932	1			T1	38		T3	171		T4	5
valid_sources[0x27]	27148	1			T1	11		T3	180		T4	3
valid_sources[0x28]	30547	1			T1	15		T3	187		T4	3
valid_sources[0x29]	25350	1			T1	51		T2	1		T3	176
valid_sources[0x2a]	31821	1			T1	22		T2	162		T3	184
valid_sources[0x2b]	25367	1			T1	24		T3	187		T4	4
valid_sources[0x2c]	27583	1			T1	29		T3	189		T4	3
valid_sources[0x2d]	29482	1			T1	21		T3	185		T4	4
valid_sources[0x2e]	26099	1			T1	23		T3	172		T4	8
valid_sources[0x2f]	28092	1			T1	21		T3	194		T4	2
valid_sources[0x30]	30624	1			T1	31		T3	162		T4	3
valid_sources[0x31]	31197	1			T1	21		T3	182		T4	2
valid_sources[0x32]	29330	1			T1	36		T3	158		T4	4
valid_sources[0x33]	26689	1			T1	24		T3	191		T4	2
valid_sources[0x34]	27624	1			T1	12		T3	194		T4	6
valid_sources[0x35]	26857	1			T1	27		T3	177		T4	1
valid_sources[0x36]	32304	1			T1	21		T3	185		T4	2
valid_sources[0x37]	25002	1			T1	20		T3	151		T4	3
valid_sources[0x38]	27775	1			T1	23		T3	198		T4	1
valid_sources[0x39]	26494	1			T1	29		T3	170		T4	6
valid_sources[0x3a]	33878	1			T1	23		T3	218		T4	7
valid_sources[0x3b]	27293	1			T1	27		T3	164		T4	6
valid_sources[0x3c]	35077	1			T1	36		T3	172		T4	3
valid_sources[0x3d]	26780	1			T1	36		T3	170		T4	4
valid_sources[0x3e]	26988	1			T1	32		T3	185		T4	8
valid_sources[0x3f]	28223	1			T1	19		T3	189		T4	2
valid_sources[0x40]	29146	1			T1	24		T3	176		T4	5
valid_sources[0x41]	27210	1			T1	22		T3	178		T4	3
valid_sources[0x42]	36489	1			T1	17		T3	159		T6	1
valid_sources[0x43]	27589	1			T1	9		T3	185		T4	7
valid_sources[0x44]	26154	1			T1	19		T3	172		T4	5
valid_sources[0x45]	27483	1			T1	36		T3	183		T4	6
valid_sources[0x46]	26378	1			T1	56		T3	185		T4	1
valid_sources[0x47]	26194	1			T1	54		T3	176		T4	6
valid_sources[0x48]	26728	1			T1	18		T3	215		T4	8
valid_sources[0x49]	28190	1			T1	49		T3	174		T4	9
valid_sources[0x4a]	26229	1			T1	28		T3	195		T4	5
valid_sources[0x4b]	27482	1			T1	37		T3	187		T4	3
valid_sources[0x4c]	31917	1			T1	44		T3	164		T4	6
valid_sources[0x4d]	30272	1			T1	20		T3	163		T4	1
valid_sources[0x4e]	26433	1			T1	25		T3	204		T4	6
valid_sources[0x4f]	35211	1			T1	24		T3	168		T4	8
valid_sources[0x50]	27744	1			T1	21		T3	177		T4	3
valid_sources[0x51]	27891	1			T1	19		T3	183		T4	5
valid_sources[0x52]	31812	1			T1	34		T3	178		T4	4
valid_sources[0x53]	28131	1			T1	30		T3	164		T4	2
valid_sources[0x54]	29567	1			T1	9		T3	151		T4	7
valid_sources[0x55]	27542	1			T1	7		T3	161		T4	2
valid_sources[0x56]	37792	1			T1	41		T3	183		T4	3
valid_sources[0x57]	25749	1			T1	17		T3	181		T4	2
valid_sources[0x58]	30424	1			T1	25		T3	172		T4	2
valid_sources[0x59]	28896	1			T1	28		T3	194		T4	5
valid_sources[0x5a]	27107	1			T1	19		T3	203		T4	7
valid_sources[0x5b]	27053	1			T1	14		T3	178		T4	3
valid_sources[0x5c]	28263	1			T1	30		T3	169		T4	3
valid_sources[0x5d]	33319	1			T1	33		T3	193		T4	3
valid_sources[0x5e]	27666	1			T1	39		T3	180		T4	4
valid_sources[0x5f]	29894	1			T1	10		T3	186		T4	3
valid_sources[0x60]	26803	1			T1	15		T3	182		T4	3
valid_sources[0x61]	26761	1			T1	15		T3	211		T4	8
valid_sources[0x62]	30993	1			T1	32		T3	203		T4	6
valid_sources[0x63]	26412	1			T1	21		T3	172		T4	3
valid_sources[0x64]	30643	1			T1	40		T3	176		T4	6
valid_sources[0x65]	28681	1			T1	37		T3	153		T4	5
valid_sources[0x66]	30132	1			T1	36		T3	155		T4	8
valid_sources[0x67]	28097	1			T1	34		T3	183		T4	2
valid_sources[0x68]	26264	1			T1	27		T3	148		T4	6
valid_sources[0x69]	28449	1			T1	17		T3	183		T4	2
valid_sources[0x6a]	41714	1			T1	14		T3	183		T4	3
valid_sources[0x6b]	28275	1			T1	22		T3	180		T4	4
valid_sources[0x6c]	30017	1			T1	37		T3	175		T4	7
valid_sources[0x6d]	50103	1			T1	34		T3	174		T4	5
valid_sources[0x6e]	27707	1			T1	18		T3	190		T4	5
valid_sources[0x6f]	28409	1			T1	42		T3	183		T4	2
valid_sources[0x70]	29420	1			T1	32		T3	164		T4	2
valid_sources[0x71]	25858	1			T1	37		T3	171		T4	4
valid_sources[0x72]	26629	1			T1	25		T2	1		T3	191
valid_sources[0x73]	30481	1			T1	22		T3	184		T4	4
valid_sources[0x74]	24651	1			T1	17		T3	191		T4	4
valid_sources[0x75]	30047	1			T1	16		T3	158		T4	4
valid_sources[0x76]	27801	1			T1	34		T3	195		T4	1
valid_sources[0x77]	37019	1			T1	8		T3	172		T4	2
valid_sources[0x78]	31429	1			T1	28		T3	151		T4	6
valid_sources[0x79]	28137	1			T1	25		T3	158		T4	2
valid_sources[0x7a]	26666	1			T1	31		T3	198		T4	2
valid_sources[0x7b]	29132	1			T1	16		T3	168		T4	1
valid_sources[0x7c]	25003	1			T1	20		T3	172		T4	3
valid_sources[0x7d]	28166	1			T1	23		T3	142		T4	4
valid_sources[0x7e]	30599	1			T1	42		T3	200		T4	2
valid_sources[0x7f]	27566	1			T1	39		T3	171		T4	3
valid_sources[0x80]	35661	1			T1	20		T3	175		T4	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1061262

1

T1

835

T2

99

T3

3720

values[0x0]

all_enables

biggest_size

1588379

1

T1

2703

T2

454

T3

10580

values[0x1]

all_enables

biggest_size

1563257

1

T1

2557

T2

425

T3

10141