Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3358735

1

T1

729

T2

93

T3

21473

full_word

4212288

1

T1

6095

T2

978

T3

24441

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7570673	1			T1	6824		T2	1071		T3	45914
auto[TlIntgErrCmd]	104	1			T91	9		T92	2		T93	6
auto[TlIntgErrData]	132	1			T91	13		T92	4		T93	5
auto[TlIntgErrBoth]	114	1			T91	8		T92	4		T93	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4084946

1

T1

1540

T2

189

T3

21676

auto[1]

3486077

1

T1

5284

T2

882

T3

24238

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3023239	1			T1	705		T2	90		T3	17956
auto[TlIntgErrNone]	partial	auto[1]	335169	1			T1	24		T2	3		T3	3517
auto[TlIntgErrNone]	full_word	auto[0]	1061562	1			T1	835		T2	99		T3	3720
auto[TlIntgErrNone]	full_word	auto[1]	3150703	1			T1	5260		T2	879		T3	20721
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T91	4		T93	1		T163	1
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T91	5		T92	2		T93	4
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T93	1		T100	1		T164	1
auto[TlIntgErrData]	partial	auto[0]	60	1			T91	7		T92	2		T93	4
auto[TlIntgErrData]	partial	auto[1]	61	1			T91	6		T92	1		T93	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T165	1		T166	1		T167	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T92	1		T163	1		T100	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T91	3		T92	3		T93	6
auto[TlIntgErrBoth]	partial	auto[1]	65	1			T91	5		T92	1		T93	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T168	1		T169	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T100	1		T168	1		T170	1