Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	425222587	2969879	0	0
DepthKnown_A	425222587	425090791	0	0
RvalidKnown_A	425222587	425090791	0	0
WreadyKnown_A	425222587	425090791	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425222587	2969879	0	0
T1	759295	9978	0	0
T2	113815	832	0	0
T3	153085	15801	0	0
T4	8919	1670	0	0
T5	1192	0	0	0
T6	39016	0	0	0
T7	449485	6654	0	0
T8	727194	0	0	0
T9	676824	0	0	0
T10	2528	100	0	0
T11	0	832	0	0
T12	0	1663	0	0
T13	0	832	0	0
T15	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425222587	425090791	0	0
T1	759295	759226	0	0
T2	113815	113719	0	0
T3	153085	153053	0	0
T4	8919	8829	0	0
T5	1192	1136	0	0
T6	39016	38933	0	0
T7	449485	449315	0	0
T8	727194	727100	0	0
T9	676824	676748	0	0
T10	2528	2446	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425222587	425090791	0	0
T1	759295	759226	0	0
T2	113815	113719	0	0
T3	153085	153053	0	0
T4	8919	8829	0	0
T5	1192	1136	0	0
T6	39016	38933	0	0
T7	449485	449315	0	0
T8	727194	727100	0	0
T9	676824	676748	0	0
T10	2528	2446	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425222587	425090791	0	0
T1	759295	759226	0	0
T2	113815	113719	0	0
T3	153085	153053	0	0
T4	8919	8829	0	0
T5	1192	1136	0	0
T6	39016	38933	0	0
T7	449485	449315	0	0
T8	727194	727100	0	0
T9	676824	676748	0	0
T10	2528	2446	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	425222587	3388671	0	0
DepthKnown_A	425222587	425090791	0	0
RvalidKnown_A	425222587	425090791	0	0
WreadyKnown_A	425222587	425090791	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425222587	3388671	0	0
T1	759295	4992	0	0
T2	113815	832	0	0
T3	153085	9984	0	0
T4	8919	839	0	0
T5	1192	0	0	0
T6	39016	0	0	0
T7	449485	4992	0	0
T8	727194	0	0	0
T9	676824	0	0	0
T10	2528	100	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	832	0	0
T15	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425222587	425090791	0	0
T1	759295	759226	0	0
T2	113815	113719	0	0
T3	153085	153053	0	0
T4	8919	8829	0	0
T5	1192	1136	0	0
T6	39016	38933	0	0
T7	449485	449315	0	0
T8	727194	727100	0	0
T9	676824	676748	0	0
T10	2528	2446	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425222587	425090791	0	0
T1	759295	759226	0	0
T2	113815	113719	0	0
T3	153085	153053	0	0
T4	8919	8829	0	0
T5	1192	1136	0	0
T6	39016	38933	0	0
T7	449485	449315	0	0
T8	727194	727100	0	0
T9	676824	676748	0	0
T10	2528	2446	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425222587	425090791	0	0
T1	759295	759226	0	0
T2	113815	113719	0	0
T3	153085	153053	0	0
T4	8919	8829	0	0
T5	1192	1136	0	0
T6	39016	38933	0	0
T7	449485	449315	0	0
T8	727194	727100	0	0
T9	676824	676748	0	0
T10	2528	2446	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	425222587	199805	0	0
DepthKnown_A	425222587	425090791	0	0
RvalidKnown_A	425222587	425090791	0	0
WreadyKnown_A	425222587	425090791	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425222587	199805	0	0
T1	759295	128	0	0
T2	113815	0	0	0
T3	153085	2317	0	0
T4	8919	0	0	0
T5	1192	0	0	0
T6	39016	0	0	0
T7	449485	1358	0	0
T8	727194	907	0	0
T9	676824	0	0	0
T10	2528	100	0	0
T11	0	256	0	0
T26	0	457	0	0
T27	0	605	0	0
T31	0	100	0	0
T33	0	384	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425222587	425090791	0	0
T1	759295	759226	0	0
T2	113815	113719	0	0
T3	153085	153053	0	0
T4	8919	8829	0	0
T5	1192	1136	0	0
T6	39016	38933	0	0
T7	449485	449315	0	0
T8	727194	727100	0	0
T9	676824	676748	0	0
T10	2528	2446	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425222587	425090791	0	0
T1	759295	759226	0	0
T2	113815	113719	0	0
T3	153085	153053	0	0
T4	8919	8829	0	0
T5	1192	1136	0	0
T6	39016	38933	0	0
T7	449485	449315	0	0
T8	727194	727100	0	0
T9	676824	676748	0	0
T10	2528	2446	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425222587	425090791	0	0
T1	759295	759226	0	0
T2	113815	113719	0	0
T3	153085	153053	0	0
T4	8919	8829	0	0
T5	1192	1136	0	0
T6	39016	38933	0	0
T7	449485	449315	0	0
T8	727194	727100	0	0
T9	676824	676748	0	0
T10	2528	2446	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	425222587	447071	0	0
DepthKnown_A	425222587	425090791	0	0
RvalidKnown_A	425222587	425090791	0	0
WreadyKnown_A	425222587	425090791	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425222587	447071	0	0
T1	759295	128	0	0
T2	113815	0	0	0
T3	153085	2317	0	0
T4	8919	0	0	0
T5	1192	0	0	0
T6	39016	0	0	0
T7	449485	1358	0	0
T8	727194	907	0	0
T9	676824	0	0	0
T10	2528	100	0	0
T11	0	256	0	0
T26	0	457	0	0
T27	0	2721	0	0
T31	0	100	0	0
T33	0	1284	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425222587	425090791	0	0
T1	759295	759226	0	0
T2	113815	113719	0	0
T3	153085	153053	0	0
T4	8919	8829	0	0
T5	1192	1136	0	0
T6	39016	38933	0	0
T7	449485	449315	0	0
T8	727194	727100	0	0
T9	676824	676748	0	0
T10	2528	2446	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425222587	425090791	0	0
T1	759295	759226	0	0
T2	113815	113719	0	0
T3	153085	153053	0	0
T4	8919	8829	0	0
T5	1192	1136	0	0
T6	39016	38933	0	0
T7	449485	449315	0	0
T8	727194	727100	0	0
T9	676824	676748	0	0
T10	2528	2446	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425222587	425090791	0	0
T1	759295	759226	0	0
T2	113815	113719	0	0
T3	153085	153053	0	0
T4	8919	8829	0	0
T5	1192	1136	0	0
T6	39016	38933	0	0
T7	449485	449315	0	0
T8	727194	727100	0	0
T9	676824	676748	0	0
T10	2528	2446	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	425222587	5773824	0	0
DepthKnown_A	425222587	425090791	0	0
RvalidKnown_A	425222587	425090791	0	0
WreadyKnown_A	425222587	425090791	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425222587	5773824	0	0
T1	759295	1708	0	0
T2	113815	240	0	0
T3	153085	33850	0	0
T4	8919	175	0	0
T5	1192	3	0	0
T6	39016	157	0	0
T7	449485	10939	0	0
T8	727194	11756	0	0
T9	676824	736	0	0
T10	2528	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425222587	425090791	0	0
T1	759295	759226	0	0
T2	113815	113719	0	0
T3	153085	153053	0	0
T4	8919	8829	0	0
T5	1192	1136	0	0
T6	39016	38933	0	0
T7	449485	449315	0	0
T8	727194	727100	0	0
T9	676824	676748	0	0
T10	2528	2446	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425222587	425090791	0	0
T1	759295	759226	0	0
T2	113815	113719	0	0
T3	153085	153053	0	0
T4	8919	8829	0	0
T5	1192	1136	0	0
T6	39016	38933	0	0
T7	449485	449315	0	0
T8	727194	727100	0	0
T9	676824	676748	0	0
T10	2528	2446	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425222587	425090791	0	0
T1	759295	759226	0	0
T2	113815	113719	0	0
T3	153085	153053	0	0
T4	8919	8829	0	0
T5	1192	1136	0	0
T6	39016	38933	0	0
T7	449485	449315	0	0
T8	727194	727100	0	0
T9	676824	676748	0	0
T10	2528	2446	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	425222587	11589277	0	0
DepthKnown_A	425222587	425090791	0	0
RvalidKnown_A	425222587	425090791	0	0
WreadyKnown_A	425222587	425090791	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425222587	11589277	0	0
T1	759295	1704	0	0
T2	113815	239	0	0
T3	153085	33613	0	0
T4	8919	779	0	0
T5	1192	3	0	0
T6	39016	730	0	0
T7	449485	10884	0	0
T8	727194	11744	0	0
T9	676824	736	0	0
T10	2528	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425222587	425090791	0	0
T1	759295	759226	0	0
T2	113815	113719	0	0
T3	153085	153053	0	0
T4	8919	8829	0	0
T5	1192	1136	0	0
T6	39016	38933	0	0
T7	449485	449315	0	0
T8	727194	727100	0	0
T9	676824	676748	0	0
T10	2528	2446	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425222587	425090791	0	0
T1	759295	759226	0	0
T2	113815	113719	0	0
T3	153085	153053	0	0
T4	8919	8829	0	0
T5	1192	1136	0	0
T6	39016	38933	0	0
T7	449485	449315	0	0
T8	727194	727100	0	0
T9	676824	676748	0	0
T10	2528	2446	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425222587	425090791	0	0
T1	759295	759226	0	0
T2	113815	113719	0	0
T3	153085	153053	0	0
T4	8919	8829	0	0
T5	1192	1136	0	0
T6	39016	38933	0	0
T7	449485	449315	0	0
T8	727194	727100	0	0
T9	676824	676748	0	0
T10	2528	2446	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0