Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T8
1	0	Covered	T3,T7,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Unreachable
1	1	Covered	T3,T7,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	723605751	571839672	0	0
CheckNGreaterZero_A	2928	2928	0	0
GntImpliesReady_A	723605751	3770244	0	0
GntImpliesValid_A	723605751	3770244	0	0
GrantKnown_A	723605751	571839672	0	0
IdxKnown_A	723605751	571839672	0	0
IndexIsCorrect_A	723605751	3770244	0	0
LockArbDecision_A	723605751	0	0	0
NoReadyValidNoGrant_A	723605751	0	0	0
ReadyAndValidImplyGrant_A	723605751	3770244	0	0
ReqAndReadyImplyGrant_A	723605751	3770244	0	0
ReqImpliesValid_A	723605751	3770244	0	0
ReqStaysHighUntilGranted0_M	723605751	0	0	0
RoundRobin_A	723605751	1	0	976
ValidKnown_A	723605751	571839672	0	0
gen_data_port_assertion.DataFlow_A	723605751	3770244	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	723605751	571839672	0	0
T1	1007608	1005526	0	0
T2	127639	127543	0	0
T3	359951	1173773	0	0
T4	40631	24685	0	0
T5	1192	1136	0	0
T6	105964	70573	0	0
T7	2046771	1240991	0	0
T8	971008	844540	0	0
T9	848308	759420	0	0
T10	2528	2446	0	0
T11	311910	155546	0	0
T12	40982	20491	0	0
T13	78688	78348	0	0
T15	16425	16319	0	0
T16	0	38516	0	0
T24	0	99904	0	0
T25	0	936	0	0
T26	0	102776	0	0
T27	0	75584	0	0
T28	0	227208	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2928	2928	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	723605751	3770244	0	0
T1	1007608	5906	0	0
T2	127639	832	0	0
T3	359951	34819	0	0
T4	40631	832	0	0
T5	1192	0	0	0
T6	105964	0	0	0
T7	2046771	18268	0	0
T8	971008	7303	0	0
T9	848308	0	0	0
T10	2528	200	0	0
T11	311910	2128	0	0
T12	40982	832	0	0
T13	78688	832	0	0
T15	16425	0	0	0
T18	0	7117	0	0
T26	0	2887	0	0
T27	0	3505	0	0
T28	0	5726	0	0
T33	0	1828	0	0
T38	0	2137	0	0
T40	0	7701	0	0
T45	0	101	0	0
T46	0	80	0	0
T47	0	2287	0	0
T48	0	1074	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	723605751	3770244	0	0
T1	1007608	5906	0	0
T2	127639	832	0	0
T3	359951	34819	0	0
T4	40631	832	0	0
T5	1192	0	0	0
T6	105964	0	0	0
T7	2046771	18268	0	0
T8	971008	7303	0	0
T9	848308	0	0	0
T10	2528	200	0	0
T11	311910	2128	0	0
T12	40982	832	0	0
T13	78688	832	0	0
T15	16425	0	0	0
T18	0	7117	0	0
T26	0	2887	0	0
T27	0	3505	0	0
T28	0	5726	0	0
T33	0	1828	0	0
T38	0	2137	0	0
T40	0	7701	0	0
T45	0	101	0	0
T46	0	80	0	0
T47	0	2287	0	0
T48	0	1074	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	723605751	571839672	0	0
T1	1007608	1005526	0	0
T2	127639	127543	0	0
T3	359951	1173773	0	0
T4	40631	24685	0	0
T5	1192	1136	0	0
T6	105964	70573	0	0
T7	2046771	1240991	0	0
T8	971008	844540	0	0
T9	848308	759420	0	0
T10	2528	2446	0	0
T11	311910	155546	0	0
T12	40982	20491	0	0
T13	78688	78348	0	0
T15	16425	16319	0	0
T16	0	38516	0	0
T24	0	99904	0	0
T25	0	936	0	0
T26	0	102776	0	0
T27	0	75584	0	0
T28	0	227208	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	723605751	571839672	0	0
T1	1007608	1005526	0	0
T2	127639	127543	0	0
T3	359951	1173773	0	0
T4	40631	24685	0	0
T5	1192	1136	0	0
T6	105964	70573	0	0
T7	2046771	1240991	0	0
T8	971008	844540	0	0
T9	848308	759420	0	0
T10	2528	2446	0	0
T11	311910	155546	0	0
T12	40982	20491	0	0
T13	78688	78348	0	0
T15	16425	16319	0	0
T16	0	38516	0	0
T24	0	99904	0	0
T25	0	936	0	0
T26	0	102776	0	0
T27	0	75584	0	0
T28	0	227208	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	723605751	3770244	0	0
T1	1007608	5906	0	0
T2	127639	832	0	0
T3	359951	34819	0	0
T4	40631	832	0	0
T5	1192	0	0	0
T6	105964	0	0	0
T7	2046771	18268	0	0
T8	971008	7303	0	0
T9	848308	0	0	0
T10	2528	200	0	0
T11	311910	2128	0	0
T12	40982	832	0	0
T13	78688	832	0	0
T15	16425	0	0	0
T18	0	7117	0	0
T26	0	2887	0	0
T27	0	3505	0	0
T28	0	5726	0	0
T33	0	1828	0	0
T38	0	2137	0	0
T40	0	7701	0	0
T45	0	101	0	0
T46	0	80	0	0
T47	0	2287	0	0
T48	0	1074	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	723605751	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	723605751	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	723605751	3770244	0	0
T1	1007608	5906	0	0
T2	127639	832	0	0
T3	359951	34819	0	0
T4	40631	832	0	0
T5	1192	0	0	0
T6	105964	0	0	0
T7	2046771	18268	0	0
T8	971008	7303	0	0
T9	848308	0	0	0
T10	2528	200	0	0
T11	311910	2128	0	0
T12	40982	832	0	0
T13	78688	832	0	0
T15	16425	0	0	0
T18	0	7117	0	0
T26	0	2887	0	0
T27	0	3505	0	0
T28	0	5726	0	0
T33	0	1828	0	0
T38	0	2137	0	0
T40	0	7701	0	0
T45	0	101	0	0
T46	0	80	0	0
T47	0	2287	0	0
T48	0	1074	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	723605751	3770244	0	0
T1	1007608	5906	0	0
T2	127639	832	0	0
T3	359951	34819	0	0
T4	40631	832	0	0
T5	1192	0	0	0
T6	105964	0	0	0
T7	2046771	18268	0	0
T8	971008	7303	0	0
T9	848308	0	0	0
T10	2528	200	0	0
T11	311910	2128	0	0
T12	40982	832	0	0
T13	78688	832	0	0
T15	16425	0	0	0
T18	0	7117	0	0
T26	0	2887	0	0
T27	0	3505	0	0
T28	0	5726	0	0
T33	0	1828	0	0
T38	0	2137	0	0
T40	0	7701	0	0
T45	0	101	0	0
T46	0	80	0	0
T47	0	2287	0	0
T48	0	1074	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	723605751	3770244	0	0
T1	1007608	5906	0	0
T2	127639	832	0	0
T3	359951	34819	0	0
T4	40631	832	0	0
T5	1192	0	0	0
T6	105964	0	0	0
T7	2046771	18268	0	0
T8	971008	7303	0	0
T9	848308	0	0	0
T10	2528	200	0	0
T11	311910	2128	0	0
T12	40982	832	0	0
T13	78688	832	0	0
T15	16425	0	0	0
T18	0	7117	0	0
T26	0	2887	0	0
T27	0	3505	0	0
T28	0	5726	0	0
T33	0	1828	0	0
T38	0	2137	0	0
T40	0	7701	0	0
T45	0	101	0	0
T46	0	80	0	0
T47	0	2287	0	0
T48	0	1074	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	723605751	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	723605751	1	0	976
T49	518756	1	0	1
T50	324697	0	0	1
T51	503610	0	0	1
T52	9410	0	0	1
T53	265475	0	0	1
T54	365478	0	0	1
T55	291086	0	0	1
T56	38641	0	0	1
T57	1355	0	0	1
T58	392482	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	723605751	571839672	0	0
T1	1007608	1005526	0	0
T2	127639	127543	0	0
T3	359951	1173773	0	0
T4	40631	24685	0	0
T5	1192	1136	0	0
T6	105964	70573	0	0
T7	2046771	1240991	0	0
T8	971008	844540	0	0
T9	848308	759420	0	0
T10	2528	2446	0	0
T11	311910	155546	0	0
T12	40982	20491	0	0
T13	78688	78348	0	0
T15	16425	16319	0	0
T16	0	38516	0	0
T24	0	99904	0	0
T25	0	936	0	0
T26	0	102776	0	0
T27	0	75584	0	0
T28	0	227208	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	723605751	3770244	0	0
T1	1007608	5906	0	0
T2	127639	832	0	0
T3	359951	34819	0	0
T4	40631	832	0	0
T5	1192	0	0	0
T6	105964	0	0	0
T7	2046771	18268	0	0
T8	971008	7303	0	0
T9	848308	0	0	0
T10	2528	200	0	0
T11	311910	2128	0	0
T12	40982	832	0	0
T13	78688	832	0	0
T15	16425	0	0	0
T18	0	7117	0	0
T26	0	2887	0	0
T27	0	3505	0	0
T28	0	5726	0	0
T33	0	1828	0	0
T38	0	2137	0	0
T40	0	7701	0	0
T45	0	101	0	0
T46	0	80	0	0
T47	0	2287	0	0
T48	0	1074	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T8
1	0	Covered	T3,T7,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Unreachable
1	1	Covered	T3,T7,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T7,T8
0	0	1	Unreachable
0	0	0	Covered	T3,T6,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	150237577	29899027	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	150237577	661216	0	0
GntImpliesValid_A	150237577	661216	0	0
GrantKnown_A	150237577	29899027	0	0
IdxKnown_A	150237577	29899027	0	0
IndexIsCorrect_A	150237577	661216	0	0
LockArbDecision_A	150237577	0	0	0
NoReadyValidNoGrant_A	150237577	0	0	0
ReadyAndValidImplyGrant_A	150237577	661216	0	0
ReqAndReadyImplyGrant_A	150237577	661216	0	0
ReqImpliesValid_A	150237577	661216	0	0
ReqStaysHighUntilGranted0_M	150237577	0	0	0
RoundRobin_A	150237577	0	0	0
ValidKnown_A	150237577	29899027	0	0
gen_data_port_assertion.DataFlow_A	150237577	661216	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150237577	29899027	0	0
T3	103433	466752	0	0
T4	15856	0	0	0
T6	33474	31640	0	0
T7	798643	312720	0	0
T8	121907	117440	0	0
T9	85742	82672	0	0
T11	155955	0	0	0
T12	20491	0	0	0
T13	78688	0	0	0
T15	16425	0	0	0
T24	0	99904	0	0
T25	0	936	0	0
T26	0	102776	0	0
T27	0	75584	0	0
T28	0	227208	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150237577	661216	0	0
T3	103433	10140	0	0
T4	15856	0	0	0
T6	33474	0	0	0
T7	798643	5553	0	0
T8	121907	5017	0	0
T9	85742	0	0	0
T11	155955	0	0	0
T12	20491	0	0	0
T13	78688	0	0	0
T15	16425	0	0	0
T18	0	2750	0	0
T26	0	2887	0	0
T27	0	3505	0	0
T28	0	5726	0	0
T45	0	101	0	0
T46	0	80	0	0
T47	0	2287	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150237577	661216	0	0
T3	103433	10140	0	0
T4	15856	0	0	0
T6	33474	0	0	0
T7	798643	5553	0	0
T8	121907	5017	0	0
T9	85742	0	0	0
T11	155955	0	0	0
T12	20491	0	0	0
T13	78688	0	0	0
T15	16425	0	0	0
T18	0	2750	0	0
T26	0	2887	0	0
T27	0	3505	0	0
T28	0	5726	0	0
T45	0	101	0	0
T46	0	80	0	0
T47	0	2287	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150237577	29899027	0	0
T3	103433	466752	0	0
T4	15856	0	0	0
T6	33474	31640	0	0
T7	798643	312720	0	0
T8	121907	117440	0	0
T9	85742	82672	0	0
T11	155955	0	0	0
T12	20491	0	0	0
T13	78688	0	0	0
T15	16425	0	0	0
T24	0	99904	0	0
T25	0	936	0	0
T26	0	102776	0	0
T27	0	75584	0	0
T28	0	227208	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150237577	29899027	0	0
T3	103433	466752	0	0
T4	15856	0	0	0
T6	33474	31640	0	0
T7	798643	312720	0	0
T8	121907	117440	0	0
T9	85742	82672	0	0
T11	155955	0	0	0
T12	20491	0	0	0
T13	78688	0	0	0
T15	16425	0	0	0
T24	0	99904	0	0
T25	0	936	0	0
T26	0	102776	0	0
T27	0	75584	0	0
T28	0	227208	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150237577	661216	0	0
T3	103433	10140	0	0
T4	15856	0	0	0
T6	33474	0	0	0
T7	798643	5553	0	0
T8	121907	5017	0	0
T9	85742	0	0	0
T11	155955	0	0	0
T12	20491	0	0	0
T13	78688	0	0	0
T15	16425	0	0	0
T18	0	2750	0	0
T26	0	2887	0	0
T27	0	3505	0	0
T28	0	5726	0	0
T45	0	101	0	0
T46	0	80	0	0
T47	0	2287	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150237577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150237577	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150237577	661216	0	0
T3	103433	10140	0	0
T4	15856	0	0	0
T6	33474	0	0	0
T7	798643	5553	0	0
T8	121907	5017	0	0
T9	85742	0	0	0
T11	155955	0	0	0
T12	20491	0	0	0
T13	78688	0	0	0
T15	16425	0	0	0
T18	0	2750	0	0
T26	0	2887	0	0
T27	0	3505	0	0
T28	0	5726	0	0
T45	0	101	0	0
T46	0	80	0	0
T47	0	2287	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150237577	661216	0	0
T3	103433	10140	0	0
T4	15856	0	0	0
T6	33474	0	0	0
T7	798643	5553	0	0
T8	121907	5017	0	0
T9	85742	0	0	0
T11	155955	0	0	0
T12	20491	0	0	0
T13	78688	0	0	0
T15	16425	0	0	0
T18	0	2750	0	0
T26	0	2887	0	0
T27	0	3505	0	0
T28	0	5726	0	0
T45	0	101	0	0
T46	0	80	0	0
T47	0	2287	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150237577	661216	0	0
T3	103433	10140	0	0
T4	15856	0	0	0
T6	33474	0	0	0
T7	798643	5553	0	0
T8	121907	5017	0	0
T9	85742	0	0	0
T11	155955	0	0	0
T12	20491	0	0	0
T13	78688	0	0	0
T15	16425	0	0	0
T18	0	2750	0	0
T26	0	2887	0	0
T27	0	3505	0	0
T28	0	5726	0	0
T45	0	101	0	0
T46	0	80	0	0
T47	0	2287	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	150237577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150237577	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150237577	29899027	0	0
T3	103433	466752	0	0
T4	15856	0	0	0
T6	33474	31640	0	0
T7	798643	312720	0	0
T8	121907	117440	0	0
T9	85742	82672	0	0
T11	155955	0	0	0
T12	20491	0	0	0
T13	78688	0	0	0
T15	16425	0	0	0
T24	0	99904	0	0
T25	0	936	0	0
T26	0	102776	0	0
T27	0	75584	0	0
T28	0	227208	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150237577	661216	0	0
T3	103433	10140	0	0
T4	15856	0	0	0
T6	33474	0	0	0
T7	798643	5553	0	0
T8	121907	5017	0	0
T9	85742	0	0	0
T11	155955	0	0	0
T12	20491	0	0	0
T13	78688	0	0	0
T15	16425	0	0	0
T18	0	2750	0	0
T26	0	2887	0	0
T27	0	3505	0	0
T28	0	5726	0	0
T45	0	101	0	0
T46	0	80	0	0
T47	0	2287	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	150237577	118900245	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	150237577	779085	0	0
GntImpliesValid_A	150237577	779085	0	0
GrantKnown_A	150237577	118900245	0	0
IdxKnown_A	150237577	118900245	0	0
IndexIsCorrect_A	150237577	779085	0	0
LockArbDecision_A	150237577	0	0	0
NoReadyValidNoGrant_A	150237577	0	0	0
ReadyAndValidImplyGrant_A	150237577	779085	0	0
ReqAndReadyImplyGrant_A	150237577	779085	0	0
ReqImpliesValid_A	150237577	779085	0	0
ReqStaysHighUntilGranted0_M	150237577	0	0	0
RoundRobin_A	150237577	0	0	0
ValidKnown_A	150237577	118900245	0	0
gen_data_port_assertion.DataFlow_A	150237577	779085	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150237577	118900245	0	0
T1	248313	246300	0	0
T2	13824	13824	0	0
T3	103433	553968	0	0
T4	15856	15856	0	0
T6	33474	0	0	0
T7	798643	478956	0	0
T8	121907	0	0	0
T9	85742	0	0	0
T11	155955	155546	0	0
T12	20491	20491	0	0
T13	0	78348	0	0
T15	0	16319	0	0
T16	0	38516	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150237577	779085	0	0
T1	248313	777	0	0
T2	13824	0	0	0
T3	103433	8982	0	0
T4	15856	0	0	0
T6	33474	0	0	0
T7	798643	4470	0	0
T8	121907	0	0	0
T9	85742	0	0	0
T11	155955	1032	0	0
T12	20491	0	0	0
T18	0	4367	0	0
T33	0	1828	0	0
T38	0	2137	0	0
T40	0	7701	0	0
T48	0	1074	0	0
T59	0	523	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150237577	779085	0	0
T1	248313	777	0	0
T2	13824	0	0	0
T3	103433	8982	0	0
T4	15856	0	0	0
T6	33474	0	0	0
T7	798643	4470	0	0
T8	121907	0	0	0
T9	85742	0	0	0
T11	155955	1032	0	0
T12	20491	0	0	0
T18	0	4367	0	0
T33	0	1828	0	0
T38	0	2137	0	0
T40	0	7701	0	0
T48	0	1074	0	0
T59	0	523	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150237577	118900245	0	0
T1	248313	246300	0	0
T2	13824	13824	0	0
T3	103433	553968	0	0
T4	15856	15856	0	0
T6	33474	0	0	0
T7	798643	478956	0	0
T8	121907	0	0	0
T9	85742	0	0	0
T11	155955	155546	0	0
T12	20491	20491	0	0
T13	0	78348	0	0
T15	0	16319	0	0
T16	0	38516	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150237577	118900245	0	0
T1	248313	246300	0	0
T2	13824	13824	0	0
T3	103433	553968	0	0
T4	15856	15856	0	0
T6	33474	0	0	0
T7	798643	478956	0	0
T8	121907	0	0	0
T9	85742	0	0	0
T11	155955	155546	0	0
T12	20491	20491	0	0
T13	0	78348	0	0
T15	0	16319	0	0
T16	0	38516	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150237577	779085	0	0
T1	248313	777	0	0
T2	13824	0	0	0
T3	103433	8982	0	0
T4	15856	0	0	0
T6	33474	0	0	0
T7	798643	4470	0	0
T8	121907	0	0	0
T9	85742	0	0	0
T11	155955	1032	0	0
T12	20491	0	0	0
T18	0	4367	0	0
T33	0	1828	0	0
T38	0	2137	0	0
T40	0	7701	0	0
T48	0	1074	0	0
T59	0	523	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150237577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150237577	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150237577	779085	0	0
T1	248313	777	0	0
T2	13824	0	0	0
T3	103433	8982	0	0
T4	15856	0	0	0
T6	33474	0	0	0
T7	798643	4470	0	0
T8	121907	0	0	0
T9	85742	0	0	0
T11	155955	1032	0	0
T12	20491	0	0	0
T18	0	4367	0	0
T33	0	1828	0	0
T38	0	2137	0	0
T40	0	7701	0	0
T48	0	1074	0	0
T59	0	523	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150237577	779085	0	0
T1	248313	777	0	0
T2	13824	0	0	0
T3	103433	8982	0	0
T4	15856	0	0	0
T6	33474	0	0	0
T7	798643	4470	0	0
T8	121907	0	0	0
T9	85742	0	0	0
T11	155955	1032	0	0
T12	20491	0	0	0
T18	0	4367	0	0
T33	0	1828	0	0
T38	0	2137	0	0
T40	0	7701	0	0
T48	0	1074	0	0
T59	0	523	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150237577	779085	0	0
T1	248313	777	0	0
T2	13824	0	0	0
T3	103433	8982	0	0
T4	15856	0	0	0
T6	33474	0	0	0
T7	798643	4470	0	0
T8	121907	0	0	0
T9	85742	0	0	0
T11	155955	1032	0	0
T12	20491	0	0	0
T18	0	4367	0	0
T33	0	1828	0	0
T38	0	2137	0	0
T40	0	7701	0	0
T48	0	1074	0	0
T59	0	523	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	150237577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150237577	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150237577	118900245	0	0
T1	248313	246300	0	0
T2	13824	13824	0	0
T3	103433	553968	0	0
T4	15856	15856	0	0
T6	33474	0	0	0
T7	798643	478956	0	0
T8	121907	0	0	0
T9	85742	0	0	0
T11	155955	155546	0	0
T12	20491	20491	0	0
T13	0	78348	0	0
T15	0	16319	0	0
T16	0	38516	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150237577	779085	0	0
T1	248313	777	0	0
T2	13824	0	0	0
T3	103433	8982	0	0
T4	15856	0	0	0
T6	33474	0	0	0
T7	798643	4470	0	0
T8	121907	0	0	0
T9	85742	0	0	0
T11	155955	1032	0	0
T12	20491	0	0	0
T18	0	4367	0	0
T33	0	1828	0	0
T38	0	2137	0	0
T40	0	7701	0	0
T48	0	1074	0	0
T59	0	523	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423130597	423040400	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	423130597	2329943	0	0
GntImpliesValid_A	423130597	2329943	0	0
GrantKnown_A	423130597	423040400	0	0
IdxKnown_A	423130597	423040400	0	0
IndexIsCorrect_A	423130597	2329943	0	0
LockArbDecision_A	423130597	0	0	0
NoReadyValidNoGrant_A	423130597	0	0	0
ReadyAndValidImplyGrant_A	423130597	2329943	0	0
ReqAndReadyImplyGrant_A	423130597	2329943	0	0
ReqImpliesValid_A	423130597	2329943	0	0
ReqStaysHighUntilGranted0_M	423130597	0	0	0
RoundRobin_A	423130597	1	0	976
ValidKnown_A	423130597	423040400	0	0
gen_data_port_assertion.DataFlow_A	423130597	2329943	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423130597	423040400	0	0
T1	759295	759226	0	0
T2	113815	113719	0	0
T3	153085	153053	0	0
T4	8919	8829	0	0
T5	1192	1136	0	0
T6	39016	38933	0	0
T7	449485	449315	0	0
T8	727194	727100	0	0
T9	676824	676748	0	0
T10	2528	2446	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423130597	2329943	0	0
T1	759295	5129	0	0
T2	113815	832	0	0
T3	153085	15697	0	0
T4	8919	832	0	0
T5	1192	0	0	0
T6	39016	0	0	0
T7	449485	8245	0	0
T8	727194	2286	0	0
T9	676824	0	0	0
T10	2528	200	0	0
T11	0	1096	0	0
T12	0	832	0	0
T13	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423130597	2329943	0	0
T1	759295	5129	0	0
T2	113815	832	0	0
T3	153085	15697	0	0
T4	8919	832	0	0
T5	1192	0	0	0
T6	39016	0	0	0
T7	449485	8245	0	0
T8	727194	2286	0	0
T9	676824	0	0	0
T10	2528	200	0	0
T11	0	1096	0	0
T12	0	832	0	0
T13	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423130597	423040400	0	0
T1	759295	759226	0	0
T2	113815	113719	0	0
T3	153085	153053	0	0
T4	8919	8829	0	0
T5	1192	1136	0	0
T6	39016	38933	0	0
T7	449485	449315	0	0
T8	727194	727100	0	0
T9	676824	676748	0	0
T10	2528	2446	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423130597	423040400	0	0
T1	759295	759226	0	0
T2	113815	113719	0	0
T3	153085	153053	0	0
T4	8919	8829	0	0
T5	1192	1136	0	0
T6	39016	38933	0	0
T7	449485	449315	0	0
T8	727194	727100	0	0
T9	676824	676748	0	0
T10	2528	2446	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423130597	2329943	0	0
T1	759295	5129	0	0
T2	113815	832	0	0
T3	153085	15697	0	0
T4	8919	832	0	0
T5	1192	0	0	0
T6	39016	0	0	0
T7	449485	8245	0	0
T8	727194	2286	0	0
T9	676824	0	0	0
T10	2528	200	0	0
T11	0	1096	0	0
T12	0	832	0	0
T13	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423130597	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423130597	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423130597	2329943	0	0
T1	759295	5129	0	0
T2	113815	832	0	0
T3	153085	15697	0	0
T4	8919	832	0	0
T5	1192	0	0	0
T6	39016	0	0	0
T7	449485	8245	0	0
T8	727194	2286	0	0
T9	676824	0	0	0
T10	2528	200	0	0
T11	0	1096	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423130597	2329943	0	0
T1	759295	5129	0	0
T2	113815	832	0	0
T3	153085	15697	0	0
T4	8919	832	0	0
T5	1192	0	0	0
T6	39016	0	0	0
T7	449485	8245	0	0
T8	727194	2286	0	0
T9	676824	0	0	0
T10	2528	200	0	0
T11	0	1096	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423130597	2329943	0	0
T1	759295	5129	0	0
T2	113815	832	0	0
T3	153085	15697	0	0
T4	8919	832	0	0
T5	1192	0	0	0
T6	39016	0	0	0
T7	449485	8245	0	0
T8	727194	2286	0	0
T9	676824	0	0	0
T10	2528	200	0	0
T11	0	1096	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	423130597	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423130597	1	0	976
T49	518756	1	0	1
T50	324697	0	0	1
T51	503610	0	0	1
T52	9410	0	0	1
T53	265475	0	0	1
T54	365478	0	0	1
T55	291086	0	0	1
T56	38641	0	0	1
T57	1355	0	0	1
T58	392482	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423130597	423040400	0	0
T1	759295	759226	0	0
T2	113815	113719	0	0
T3	153085	153053	0	0
T4	8919	8829	0	0
T5	1192	1136	0	0
T6	39016	38933	0	0
T7	449485	449315	0	0
T8	727194	727100	0	0
T9	676824	676748	0	0
T10	2528	2446	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423130597	2329943	0	0
T1	759295	5129	0	0
T2	113815	832	0	0
T3	153085	15697	0	0
T4	8919	832	0	0
T5	1192	0	0	0
T6	39016	0	0	0
T7	449485	8245	0	0
T8	727194	2286	0	0
T9	676824	0	0	0
T10	2528	200	0	0
T11	0	1096	0	0
T12	0	832	0	0
T13	0	832	0	0