Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2997240	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3770642

1

T1

1

T2

56

T3

13586

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3736260	1			T1	1		T2	240		T3	6940
values[0x0]	1514935	1			T1	1		T2	24		T3	6700
values[0x1]	1516687	1			T2	23		T3	6622		T4	6874

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2143780	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4624102

1

T1

1

T2

130

T3

15388

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26888	1			T3	77		T5	1		T7	41
valid_sources[0x01]	25111	1			T3	81		T7	61		T8	24
valid_sources[0x02]	27175	1			T2	3		T3	85		T4	2
valid_sources[0x03]	22518	1			T2	2		T3	79		T5	2
valid_sources[0x04]	25256	1			T3	72		T5	1		T7	67
valid_sources[0x05]	26218	1			T3	104		T4	1		T7	61
valid_sources[0x06]	23697	1			T3	72		T7	95		T8	20
valid_sources[0x07]	25912	1			T3	79		T7	84		T8	26
valid_sources[0x08]	27670	1			T2	1		T3	54		T4	2742
valid_sources[0x09]	26028	1			T2	1		T3	70		T4	7
valid_sources[0x0a]	24279	1			T3	95		T4	5		T5	1
valid_sources[0x0b]	25811	1			T2	1		T3	66		T5	10
valid_sources[0x0c]	30182	1			T2	3		T3	67		T7	114
valid_sources[0x0d]	25368	1			T2	1		T3	79		T5	1
valid_sources[0x0e]	24075	1			T3	74		T4	1		T5	1
valid_sources[0x0f]	23574	1			T2	2		T3	82		T4	36
valid_sources[0x10]	28403	1			T3	87		T4	1		T7	64
valid_sources[0x11]	26821	1			T2	5		T3	69		T4	1
valid_sources[0x12]	23148	1			T2	1		T3	98		T4	4
valid_sources[0x13]	24507	1			T2	1		T3	86		T6	2
valid_sources[0x14]	25497	1			T3	73		T4	95		T7	60
valid_sources[0x15]	35443	1			T3	76		T7	67		T8	46
valid_sources[0x16]	24497	1			T2	1		T3	87		T4	2
valid_sources[0x17]	26683	1			T2	1		T3	73		T7	100
valid_sources[0x18]	26929	1			T2	5		T3	81		T7	61
valid_sources[0x19]	29930	1			T3	81		T7	79		T8	27
valid_sources[0x1a]	23004	1			T3	79		T5	3		T7	67
valid_sources[0x1b]	23538	1			T3	79		T4	28		T7	47
valid_sources[0x1c]	40366	1			T2	1		T3	87		T5	1
valid_sources[0x1d]	31295	1			T2	2		T3	73		T4	51
valid_sources[0x1e]	23478	1			T2	1		T3	67		T7	45
valid_sources[0x1f]	23095	1			T2	1		T3	81		T7	55
valid_sources[0x20]	26187	1			T3	76		T7	36		T8	21
valid_sources[0x21]	24968	1			T2	2		T3	74		T4	1
valid_sources[0x22]	25484	1			T2	1		T3	63		T4	1
valid_sources[0x23]	26035	1			T3	86		T7	128		T8	31
valid_sources[0x24]	37918	1			T2	3		T3	91		T7	78
valid_sources[0x25]	53719	1			T2	1		T3	95		T4	49
valid_sources[0x26]	25298	1			T3	94		T4	13		T7	66
valid_sources[0x27]	23377	1			T2	2		T3	74		T7	42
valid_sources[0x28]	25146	1			T3	72		T5	1		T7	38
valid_sources[0x29]	23808	1			T2	3		T3	72		T4	1
valid_sources[0x2a]	30617	1			T3	82		T4	2		T7	61
valid_sources[0x2b]	29234	1			T3	88		T7	75		T8	29
valid_sources[0x2c]	23583	1			T2	1		T3	88		T4	1
valid_sources[0x2d]	25396	1			T3	77		T7	83		T8	19
valid_sources[0x2e]	34823	1			T3	66		T4	4		T5	1
valid_sources[0x2f]	24987	1			T2	1		T3	87		T4	6
valid_sources[0x30]	24686	1			T2	2		T3	98		T7	55
valid_sources[0x31]	25330	1			T3	80		T7	112		T8	27
valid_sources[0x32]	25459	1			T2	2		T3	93		T6	1
valid_sources[0x33]	27701	1			T3	73		T4	6		T7	75
valid_sources[0x34]	25708	1			T3	77		T5	1		T7	94
valid_sources[0x35]	25821	1			T3	82		T4	651		T7	70
valid_sources[0x36]	24845	1			T2	1		T3	78		T4	2
valid_sources[0x37]	24938	1			T2	1		T3	77		T7	80
valid_sources[0x38]	23901	1			T2	1		T3	80		T7	58
valid_sources[0x39]	25311	1			T3	69		T4	1		T7	35
valid_sources[0x3a]	24347	1			T3	84		T4	417		T7	24
valid_sources[0x3b]	26083	1			T3	83		T4	1		T7	79
valid_sources[0x3c]	26460	1			T2	1		T3	73		T7	75
valid_sources[0x3d]	26847	1			T3	72		T4	1		T7	101
valid_sources[0x3e]	25151	1			T3	76		T4	1		T7	68
valid_sources[0x3f]	23507	1			T2	1		T3	89		T7	72
valid_sources[0x40]	26171	1			T2	2		T3	77		T4	1
valid_sources[0x41]	23319	1			T2	1		T3	85		T4	36
valid_sources[0x42]	26181	1			T2	1		T3	77		T4	4
valid_sources[0x43]	24500	1			T3	83		T4	1		T7	70
valid_sources[0x44]	26415	1			T2	4		T3	80		T7	35
valid_sources[0x45]	27979	1			T2	1		T3	60		T7	91
valid_sources[0x46]	26157	1			T3	83		T7	38		T8	25
valid_sources[0x47]	23572	1			T2	1		T3	84		T4	2
valid_sources[0x48]	24965	1			T3	85		T7	58		T8	46
valid_sources[0x49]	27278	1			T2	1		T3	68		T4	148
valid_sources[0x4a]	22935	1			T2	2		T3	78		T7	52
valid_sources[0x4b]	25285	1			T3	79		T4	2		T7	71
valid_sources[0x4c]	30774	1			T2	1		T3	92		T5	1
valid_sources[0x4d]	26114	1			T3	60		T4	3		T7	58
valid_sources[0x4e]	24338	1			T2	1		T3	77		T7	62
valid_sources[0x4f]	23631	1			T2	1		T3	76		T4	1
valid_sources[0x50]	27290	1			T3	79		T7	68		T8	21
valid_sources[0x51]	25429	1			T2	3		T3	88		T4	1
valid_sources[0x52]	29376	1			T2	1		T3	104		T7	43
valid_sources[0x53]	24706	1			T3	81		T4	883		T7	74
valid_sources[0x54]	27542	1			T3	85		T7	75		T8	25
valid_sources[0x55]	26414	1			T2	2		T3	94		T7	82
valid_sources[0x56]	24588	1			T2	2		T3	65		T4	89
valid_sources[0x57]	24256	1			T2	2		T3	73		T4	1564
valid_sources[0x58]	27168	1			T3	82		T7	23		T8	40
valid_sources[0x59]	26039	1			T3	102		T7	58		T8	34
valid_sources[0x5a]	29214	1			T3	83		T5	1		T7	70
valid_sources[0x5b]	26343	1			T3	68		T4	22		T7	79
valid_sources[0x5c]	33278	1			T2	2		T3	76		T4	2
valid_sources[0x5d]	27012	1			T2	2		T3	76		T4	230
valid_sources[0x5e]	36290	1			T3	66		T7	88		T8	24
valid_sources[0x5f]	25610	1			T2	1		T3	89		T7	59
valid_sources[0x60]	24699	1			T3	78		T4	1		T5	1
valid_sources[0x61]	28110	1			T2	1		T3	67		T4	13
valid_sources[0x62]	30933	1			T2	2		T3	79		T4	1
valid_sources[0x63]	28720	1			T2	1		T3	79		T7	64
valid_sources[0x64]	24472	1			T2	2		T3	92		T4	1
valid_sources[0x65]	23896	1			T2	5		T3	72		T5	3
valid_sources[0x66]	24209	1			T2	1		T3	88		T5	1
valid_sources[0x67]	25049	1			T2	2		T3	70		T4	3
valid_sources[0x68]	25780	1			T3	81		T4	2		T7	82
valid_sources[0x69]	23805	1			T2	1		T3	91		T5	1
valid_sources[0x6a]	24564	1			T3	74		T4	1		T5	1
valid_sources[0x6b]	25693	1			T2	3		T3	87		T7	64
valid_sources[0x6c]	24071	1			T2	1		T3	71		T5	2
valid_sources[0x6d]	24959	1			T2	2		T3	80		T6	1
valid_sources[0x6e]	24769	1			T3	87		T6	1		T7	61
valid_sources[0x6f]	26107	1			T2	2		T3	79		T7	81
valid_sources[0x70]	23858	1			T2	1		T3	73		T4	1
valid_sources[0x71]	27870	1			T2	2		T3	76		T7	80
valid_sources[0x72]	26264	1			T2	4		T3	70		T5	1
valid_sources[0x73]	24115	1			T2	1		T3	95		T4	1
valid_sources[0x74]	23444	1			T2	1		T3	86		T7	75
valid_sources[0x75]	25360	1			T2	2		T3	72		T5	1
valid_sources[0x76]	25663	1			T2	1		T3	85		T4	1
valid_sources[0x77]	26210	1			T2	1		T3	101		T7	78
valid_sources[0x78]	28325	1			T3	90		T7	59		T8	22
valid_sources[0x79]	24713	1			T3	81		T4	1		T7	65
valid_sources[0x7a]	23268	1			T2	3		T3	77		T5	3
valid_sources[0x7b]	23118	1			T3	99		T7	30		T8	31
valid_sources[0x7c]	26414	1			T3	75		T4	1		T7	19
valid_sources[0x7d]	25614	1			T1	2		T3	83		T7	34
valid_sources[0x7e]	25640	1			T2	1		T3	78		T7	55
valid_sources[0x7f]	22893	1			T2	2		T3	86		T7	96
valid_sources[0x80]	26083	1			T2	2		T3	73		T4	257

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1009597

1

T1

1

T2

45

T3

1838

values[0x0]

all_enables

biggest_size

1390677

1

T2

9

T3

5986

T4

6624

values[0x1]

all_enables

biggest_size

1370368

1

T2

2

T3

5762

T4

6774