Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3018616

1

T1

1

T2

231

T3

6676

full_word

3769924

1

T1

1

T2

56

T3

13586

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	6788140	1			T1	2		T2	287		T3	20262
auto[TlIntgErrCmd]	139	1			T90	8		T92	3		T95	13
auto[TlIntgErrData]	127	1			T90	5		T92	5		T95	8
auto[TlIntgErrBoth]	134	1			T90	7		T92	2		T95	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3739289

1

T1

1

T2

240

T3

6940

auto[1]

3049251

1

T1

1

T2

47

T3

13322

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	2729364	1			T2	195		T3	5102		T4	732
auto[TlIntgErrNone]	partial	auto[1]	288884	1			T1	1		T2	36		T3	1574
auto[TlIntgErrNone]	full_word	auto[0]	1009770	1			T1	1		T2	45		T3	1838
auto[TlIntgErrNone]	full_word	auto[1]	2760122	1			T2	11		T3	11748		T4	13398
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T90	5		T92	1		T95	4
auto[TlIntgErrCmd]	partial	auto[1]	80	1			T90	2		T92	1		T95	9
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T90	1		T275	1		T276	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T92	1		T271	2		T277	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T90	3		T95	4		T271	3
auto[TlIntgErrData]	partial	auto[1]	67	1			T90	1		T92	5		T95	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T95	1		T271	1		T109	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T90	1		T278	2		T272	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T90	2		T95	2		T271	2
auto[TlIntgErrBoth]	partial	auto[1]	81	1			T90	4		T92	2		T95	6
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T271	2		T274	1		T279	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T90	1		T95	1		T271	1