Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	392124215	2596668	0	0
DepthKnown_A	392124215	391989761	0	0
RvalidKnown_A	392124215	391989761	0	0
WreadyKnown_A	392124215	391989761	0	0
gen_passthru_fifo.paramCheckPass	1148	1148	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392124215	2596668	0	0
T3	404227	10812	0	0
T4	299530	15804	0	0
T5	1632	0	0	0
T6	1021	0	0	0
T7	289041	17486	0	0
T8	147402	5824	0	0
T9	27246	832	0	0
T10	25834	832	0	0
T11	58688	1663	0	0
T12	18739	832	0	0
T13	0	1663	0	0
T14	0	17489	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392124215	391989761	0	0
T1	798	709	0	0
T2	1488	1390	0	0
T3	404227	404165	0	0
T4	299530	299436	0	0
T5	1632	1582	0	0
T6	1021	962	0	0
T7	289041	289031	0	0
T8	147402	147397	0	0
T9	27246	27156	0	0
T10	25834	25778	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392124215	391989761	0	0
T1	798	709	0	0
T2	1488	1390	0	0
T3	404227	404165	0	0
T4	299530	299436	0	0
T5	1632	1582	0	0
T6	1021	962	0	0
T7	289041	289031	0	0
T8	147402	147397	0	0
T9	27246	27156	0	0
T10	25834	25778	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392124215	391989761	0	0
T1	798	709	0	0
T2	1488	1390	0	0
T3	404227	404165	0	0
T4	299530	299436	0	0
T5	1632	1582	0	0
T6	1021	962	0	0
T7	289041	289031	0	0
T8	147402	147397	0	0
T9	27246	27156	0	0
T10	25834	25778	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	392124215	2816984	0	0
DepthKnown_A	392124215	391989761	0	0
RvalidKnown_A	392124215	391989761	0	0
WreadyKnown_A	392124215	391989761	0	0
gen_passthru_fifo.paramCheckPass	1148	1148	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392124215	2816984	0	0
T3	404227	7488	0	0
T4	299530	12480	0	0
T5	1632	0	0	0
T6	1021	0	0	0
T7	289041	23884	0	0
T8	147402	9174	0	0
T9	27246	3703	0	0
T10	25834	832	0	0
T11	58688	832	0	0
T12	18739	3635	0	0
T13	0	832	0	0
T14	0	19293	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392124215	391989761	0	0
T1	798	709	0	0
T2	1488	1390	0	0
T3	404227	404165	0	0
T4	299530	299436	0	0
T5	1632	1582	0	0
T6	1021	962	0	0
T7	289041	289031	0	0
T8	147402	147397	0	0
T9	27246	27156	0	0
T10	25834	25778	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392124215	391989761	0	0
T1	798	709	0	0
T2	1488	1390	0	0
T3	404227	404165	0	0
T4	299530	299436	0	0
T5	1632	1582	0	0
T6	1021	962	0	0
T7	289041	289031	0	0
T8	147402	147397	0	0
T9	27246	27156	0	0
T10	25834	25778	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392124215	391989761	0	0
T1	798	709	0	0
T2	1488	1390	0	0
T3	404227	404165	0	0
T4	299530	299436	0	0
T5	1632	1582	0	0
T6	1021	962	0	0
T7	289041	289031	0	0
T8	147402	147397	0	0
T9	27246	27156	0	0
T10	25834	25778	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	392124215	170358	0	0
DepthKnown_A	392124215	391989761	0	0
RvalidKnown_A	392124215	391989761	0	0
WreadyKnown_A	392124215	391989761	0	0
gen_passthru_fifo.paramCheckPass	1148	1148	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392124215	170358	0	0
T2	1488	43	0	0
T3	404227	1347	0	0
T4	299530	628	0	0
T5	1632	0	0	0
T6	1021	0	0	0
T7	289041	354	0	0
T8	147402	128	0	0
T9	27246	0	0	0
T10	25834	0	0	0
T11	58688	0	0	0
T14	0	79	0	0
T30	0	998	0	0
T49	0	96	0	0
T50	0	258	0	0
T51	0	340	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392124215	391989761	0	0
T1	798	709	0	0
T2	1488	1390	0	0
T3	404227	404165	0	0
T4	299530	299436	0	0
T5	1632	1582	0	0
T6	1021	962	0	0
T7	289041	289031	0	0
T8	147402	147397	0	0
T9	27246	27156	0	0
T10	25834	25778	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392124215	391989761	0	0
T1	798	709	0	0
T2	1488	1390	0	0
T3	404227	404165	0	0
T4	299530	299436	0	0
T5	1632	1582	0	0
T6	1021	962	0	0
T7	289041	289031	0	0
T8	147402	147397	0	0
T9	27246	27156	0	0
T10	25834	25778	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392124215	391989761	0	0
T1	798	709	0	0
T2	1488	1390	0	0
T3	404227	404165	0	0
T4	299530	299436	0	0
T5	1632	1582	0	0
T6	1021	962	0	0
T7	289041	289031	0	0
T8	147402	147397	0	0
T9	27246	27156	0	0
T10	25834	25778	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	392124215	364267	0	0
DepthKnown_A	392124215	391989761	0	0
RvalidKnown_A	392124215	391989761	0	0
WreadyKnown_A	392124215	391989761	0	0
gen_passthru_fifo.paramCheckPass	1148	1148	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392124215	364267	0	0
T2	1488	43	0	0
T3	404227	1344	0	0
T4	299530	628	0	0
T5	1632	0	0	0
T6	1021	0	0	0
T7	289041	1126	0	0
T8	147402	372	0	0
T9	27246	0	0	0
T10	25834	0	0	0
T11	58688	0	0	0
T14	0	259	0	0
T30	0	998	0	0
T49	0	431	0	0
T50	0	258	0	0
T51	0	1003	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392124215	391989761	0	0
T1	798	709	0	0
T2	1488	1390	0	0
T3	404227	404165	0	0
T4	299530	299436	0	0
T5	1632	1582	0	0
T6	1021	962	0	0
T7	289041	289031	0	0
T8	147402	147397	0	0
T9	27246	27156	0	0
T10	25834	25778	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392124215	391989761	0	0
T1	798	709	0	0
T2	1488	1390	0	0
T3	404227	404165	0	0
T4	299530	299436	0	0
T5	1632	1582	0	0
T6	1021	962	0	0
T7	289041	289031	0	0
T8	147402	147397	0	0
T9	27246	27156	0	0
T10	25834	25778	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392124215	391989761	0	0
T1	798	709	0	0
T2	1488	1390	0	0
T3	404227	404165	0	0
T4	299530	299436	0	0
T5	1632	1582	0	0
T6	1021	962	0	0
T7	289041	289031	0	0
T8	147402	147397	0	0
T9	27246	27156	0	0
T10	25834	25778	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	392124215	5218860	0	0
DepthKnown_A	392124215	391989761	0	0
RvalidKnown_A	392124215	391989761	0	0
WreadyKnown_A	392124215	391989761	0	0
gen_passthru_fifo.paramCheckPass	1148	1148	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392124215	5218860	0	0
T1	798	2	0	0
T2	1488	244	0	0
T3	404227	11605	0	0
T4	299530	2138	0	0
T5	1632	79	0	0
T6	1021	14	0	0
T7	289041	4886	0	0
T8	147402	2504	0	0
T9	27246	54	0	0
T10	25834	686	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392124215	391989761	0	0
T1	798	709	0	0
T2	1488	1390	0	0
T3	404227	404165	0	0
T4	299530	299436	0	0
T5	1632	1582	0	0
T6	1021	962	0	0
T7	289041	289031	0	0
T8	147402	147397	0	0
T9	27246	27156	0	0
T10	25834	25778	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392124215	391989761	0	0
T1	798	709	0	0
T2	1488	1390	0	0
T3	404227	404165	0	0
T4	299530	299436	0	0
T5	1632	1582	0	0
T6	1021	962	0	0
T7	289041	289031	0	0
T8	147402	147397	0	0
T9	27246	27156	0	0
T10	25834	25778	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392124215	391989761	0	0
T1	798	709	0	0
T2	1488	1390	0	0
T3	404227	404165	0	0
T4	299530	299436	0	0
T5	1632	1582	0	0
T6	1021	962	0	0
T7	289041	289031	0	0
T8	147402	147397	0	0
T9	27246	27156	0	0
T10	25834	25778	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	392124215	10648996	0	0
DepthKnown_A	392124215	391989761	0	0
RvalidKnown_A	392124215	391989761	0	0
WreadyKnown_A	392124215	391989761	0	0
gen_passthru_fifo.paramCheckPass	1148	1148	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392124215	10648996	0	0
T1	798	2	0	0
T2	1488	244	0	0
T3	404227	11430	0	0
T4	299530	2128	0	0
T5	1632	357	0	0
T6	1021	75	0	0
T7	289041	15069	0	0
T8	147402	7487	0	0
T9	27246	225	0	0
T10	25834	686	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392124215	391989761	0	0
T1	798	709	0	0
T2	1488	1390	0	0
T3	404227	404165	0	0
T4	299530	299436	0	0
T5	1632	1582	0	0
T6	1021	962	0	0
T7	289041	289031	0	0
T8	147402	147397	0	0
T9	27246	27156	0	0
T10	25834	25778	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392124215	391989761	0	0
T1	798	709	0	0
T2	1488	1390	0	0
T3	404227	404165	0	0
T4	299530	299436	0	0
T5	1632	1582	0	0
T6	1021	962	0	0
T7	289041	289031	0	0
T8	147402	147397	0	0
T9	27246	27156	0	0
T10	25834	25778	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392124215	391989761	0	0
T1	798	709	0	0
T2	1488	1390	0	0
T3	404227	404165	0	0
T4	299530	299436	0	0
T5	1632	1582	0	0
T6	1021	962	0	0
T7	289041	289031	0	0
T8	147402	147397	0	0
T9	27246	27156	0	0
T10	25834	25778	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0