Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T3,T4,T30

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
1	0	Covered	T3,T4,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Unreachable
1	1	Covered	T3,T4,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	660077766	523594698	0	0
CheckNGreaterZero_A	2919	2919	0	0
GntImpliesReady_A	660077766	3309627	0	0
GntImpliesValid_A	660077766	3309627	0	0
GrantKnown_A	660077766	523594698	0	0
IdxKnown_A	660077766	523594698	0	0
IndexIsCorrect_A	660077766	3309627	0	0
LockArbDecision_A	660077766	0	0	0
NoReadyValidNoGrant_A	660077766	0	0	0
ReadyAndValidImplyGrant_A	660077766	3309627	0	0
ReqAndReadyImplyGrant_A	660077766	3309627	0	0
ReqImpliesValid_A	660077766	3309627	0	0
ReqStaysHighUntilGranted0_M	660077766	0	0	0
RoundRobin_A	660077766	3	0	973
ValidKnown_A	660077766	523594698	0	0
gen_data_port_assertion.DataFlow_A	660077766	3309627	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660077766	523594698	0	0
T1	798	709	0	0
T2	2976	2878	0	0
T3	643263	1589541	0	0
T4	1757156	1023233	0	0
T5	1632	1582	0	0
T6	1021	962	0	0
T7	2143037	1212922	0	0
T8	1105572	625885	0	0
T9	130812	78652	0	0
T10	96692	60860	0	0
T11	27648	13824	0	0
T12	42280	20840	0	0
T13	80020	39632	0	0
T14	531286	527830	0	0
T30	0	401032	0	0
T32	0	41048	0	0
T33	0	216	0	0
T35	0	78776	0	0
T36	0	72	0	0
T37	0	936	0	0
T38	0	69184	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2919	2919	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660077766	3309627	0	0
T2	2976	214	0	0
T3	643263	17920	0	0
T4	1757156	23648	0	0
T5	1632	0	0	0
T6	1021	0	0	0
T7	2143037	16221	0	0
T8	1105572	6931	0	0
T9	130812	832	0	0
T10	96692	832	0	0
T11	86336	832	0	0
T12	42280	832	0	0
T13	80020	832	0	0
T14	531286	2639	0	0
T15	0	6484	0	0
T25	0	5734	0	0
T30	0	5506	0	0
T32	0	4761	0	0
T35	0	3545	0	0
T38	0	2793	0	0
T39	0	2205	0	0
T49	0	660	0	0
T50	0	4224	0	0
T51	0	2893	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660077766	3309627	0	0
T2	2976	214	0	0
T3	643263	17920	0	0
T4	1757156	23648	0	0
T5	1632	0	0	0
T6	1021	0	0	0
T7	2143037	16221	0	0
T8	1105572	6931	0	0
T9	130812	832	0	0
T10	96692	832	0	0
T11	86336	832	0	0
T12	42280	832	0	0
T13	80020	832	0	0
T14	531286	2639	0	0
T15	0	6484	0	0
T25	0	5734	0	0
T30	0	5506	0	0
T32	0	4761	0	0
T35	0	3545	0	0
T38	0	2793	0	0
T39	0	2205	0	0
T49	0	660	0	0
T50	0	4224	0	0
T51	0	2893	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660077766	523594698	0	0
T1	798	709	0	0
T2	2976	2878	0	0
T3	643263	1589541	0	0
T4	1757156	1023233	0	0
T5	1632	1582	0	0
T6	1021	962	0	0
T7	2143037	1212922	0	0
T8	1105572	625885	0	0
T9	130812	78652	0	0
T10	96692	60860	0	0
T11	27648	13824	0	0
T12	42280	20840	0	0
T13	80020	39632	0	0
T14	531286	527830	0	0
T30	0	401032	0	0
T32	0	41048	0	0
T33	0	216	0	0
T35	0	78776	0	0
T36	0	72	0	0
T37	0	936	0	0
T38	0	69184	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660077766	523594698	0	0
T1	798	709	0	0
T2	2976	2878	0	0
T3	643263	1589541	0	0
T4	1757156	1023233	0	0
T5	1632	1582	0	0
T6	1021	962	0	0
T7	2143037	1212922	0	0
T8	1105572	625885	0	0
T9	130812	78652	0	0
T10	96692	60860	0	0
T11	27648	13824	0	0
T12	42280	20840	0	0
T13	80020	39632	0	0
T14	531286	527830	0	0
T30	0	401032	0	0
T32	0	41048	0	0
T33	0	216	0	0
T35	0	78776	0	0
T36	0	72	0	0
T37	0	936	0	0
T38	0	69184	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660077766	3309627	0	0
T2	2976	214	0	0
T3	643263	17920	0	0
T4	1757156	23648	0	0
T5	1632	0	0	0
T6	1021	0	0	0
T7	2143037	16221	0	0
T8	1105572	6931	0	0
T9	130812	832	0	0
T10	96692	832	0	0
T11	86336	832	0	0
T12	42280	832	0	0
T13	80020	832	0	0
T14	531286	2639	0	0
T15	0	6484	0	0
T25	0	5734	0	0
T30	0	5506	0	0
T32	0	4761	0	0
T35	0	3545	0	0
T38	0	2793	0	0
T39	0	2205	0	0
T49	0	660	0	0
T50	0	4224	0	0
T51	0	2893	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660077766	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660077766	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660077766	3309627	0	0
T2	2976	214	0	0
T3	643263	17920	0	0
T4	1757156	23648	0	0
T5	1632	0	0	0
T6	1021	0	0	0
T7	2143037	16221	0	0
T8	1105572	6931	0	0
T9	130812	832	0	0
T10	96692	832	0	0
T11	86336	832	0	0
T12	42280	832	0	0
T13	80020	832	0	0
T14	531286	2639	0	0
T15	0	6484	0	0
T25	0	5734	0	0
T30	0	5506	0	0
T32	0	4761	0	0
T35	0	3545	0	0
T38	0	2793	0	0
T39	0	2205	0	0
T49	0	660	0	0
T50	0	4224	0	0
T51	0	2893	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660077766	3309627	0	0
T2	2976	214	0	0
T3	643263	17920	0	0
T4	1757156	23648	0	0
T5	1632	0	0	0
T6	1021	0	0	0
T7	2143037	16221	0	0
T8	1105572	6931	0	0
T9	130812	832	0	0
T10	96692	832	0	0
T11	86336	832	0	0
T12	42280	832	0	0
T13	80020	832	0	0
T14	531286	2639	0	0
T15	0	6484	0	0
T25	0	5734	0	0
T30	0	5506	0	0
T32	0	4761	0	0
T35	0	3545	0	0
T38	0	2793	0	0
T39	0	2205	0	0
T49	0	660	0	0
T50	0	4224	0	0
T51	0	2893	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660077766	3309627	0	0
T2	2976	214	0	0
T3	643263	17920	0	0
T4	1757156	23648	0	0
T5	1632	0	0	0
T6	1021	0	0	0
T7	2143037	16221	0	0
T8	1105572	6931	0	0
T9	130812	832	0	0
T10	96692	832	0	0
T11	86336	832	0	0
T12	42280	832	0	0
T13	80020	832	0	0
T14	531286	2639	0	0
T15	0	6484	0	0
T25	0	5734	0	0
T30	0	5506	0	0
T32	0	4761	0	0
T35	0	3545	0	0
T38	0	2793	0	0
T39	0	2205	0	0
T49	0	660	0	0
T50	0	4224	0	0
T51	0	2893	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	660077766	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660077766	3	0	973
T3	404227	1	0	1
T4	299530	0	0	1
T5	1632	0	0	1
T6	1021	0	0	1
T7	289041	0	0	1
T8	147402	0	0	1
T9	27246	0	0	1
T10	25834	0	0	1
T11	58688	0	0	1
T12	18739	0	0	1
T58	0	1	0	0
T59	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660077766	523594698	0	0
T1	798	709	0	0
T2	2976	2878	0	0
T3	643263	1589541	0	0
T4	1757156	1023233	0	0
T5	1632	1582	0	0
T6	1021	962	0	0
T7	2143037	1212922	0	0
T8	1105572	625885	0	0
T9	130812	78652	0	0
T10	96692	60860	0	0
T11	27648	13824	0	0
T12	42280	20840	0	0
T13	80020	39632	0	0
T14	531286	527830	0	0
T30	0	401032	0	0
T32	0	41048	0	0
T33	0	216	0	0
T35	0	78776	0	0
T36	0	72	0	0
T37	0	936	0	0
T38	0	69184	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660077766	3309627	0	0
T2	2976	214	0	0
T3	643263	17920	0	0
T4	1757156	23648	0	0
T5	1632	0	0	0
T6	1021	0	0	0
T7	2143037	16221	0	0
T8	1105572	6931	0	0
T9	130812	832	0	0
T10	96692	832	0	0
T11	86336	832	0	0
T12	42280	832	0	0
T13	80020	832	0	0
T14	531286	2639	0	0
T15	0	6484	0	0
T25	0	5734	0	0
T30	0	5506	0	0
T32	0	4761	0	0
T35	0	3545	0	0
T38	0	2793	0	0
T39	0	2205	0	0
T49	0	660	0	0
T50	0	4224	0	0
T51	0	2893	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T3,T4,T30

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	135172308	25987786	0	0
CheckNGreaterZero_A	973	973	0	0
GntImpliesReady_A	135172308	574802	0	0
GntImpliesValid_A	135172308	574802	0	0
GrantKnown_A	135172308	25987786	0	0
IdxKnown_A	135172308	25987786	0	0
IndexIsCorrect_A	135172308	574802	0	0
LockArbDecision_A	135172308	0	0	0
NoReadyValidNoGrant_A	135172308	0	0	0
ReadyAndValidImplyGrant_A	135172308	574802	0	0
ReqAndReadyImplyGrant_A	135172308	574802	0	0
ReqImpliesValid_A	135172308	574802	0	0
ReqStaysHighUntilGranted0_M	135172308	0	0	0
RoundRobin_A	135172308	0	0	0
ValidKnown_A	135172308	25987786	0	0
gen_data_port_assertion.DataFlow_A	135172308	574802	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135172308	25987786	0	0
T2	1488	1488	0	0
T3	119518	550744	0	0
T4	728813	41224	0	0
T7	926998	0	0	0
T8	479085	0	0	0
T9	51783	0	0	0
T10	35429	0	0	0
T11	13824	0	0	0
T12	21140	0	0	0
T13	40010	0	0	0
T30	0	401032	0	0
T32	0	41048	0	0
T33	0	216	0	0
T35	0	78776	0	0
T36	0	72	0	0
T37	0	936	0	0
T38	0	69184	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973	973	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135172308	574802	0	0
T2	1488	171	0	0
T3	119518	6063	0	0
T4	728813	335	0	0
T7	926998	0	0	0
T8	479085	0	0	0
T9	51783	0	0	0
T10	35429	0	0	0
T11	13824	0	0	0
T12	21140	0	0	0
T13	40010	0	0	0
T15	0	6484	0	0
T25	0	5734	0	0
T30	0	5506	0	0
T32	0	1622	0	0
T35	0	3545	0	0
T38	0	2793	0	0
T39	0	2205	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135172308	574802	0	0
T2	1488	171	0	0
T3	119518	6063	0	0
T4	728813	335	0	0
T7	926998	0	0	0
T8	479085	0	0	0
T9	51783	0	0	0
T10	35429	0	0	0
T11	13824	0	0	0
T12	21140	0	0	0
T13	40010	0	0	0
T15	0	6484	0	0
T25	0	5734	0	0
T30	0	5506	0	0
T32	0	1622	0	0
T35	0	3545	0	0
T38	0	2793	0	0
T39	0	2205	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135172308	25987786	0	0
T2	1488	1488	0	0
T3	119518	550744	0	0
T4	728813	41224	0	0
T7	926998	0	0	0
T8	479085	0	0	0
T9	51783	0	0	0
T10	35429	0	0	0
T11	13824	0	0	0
T12	21140	0	0	0
T13	40010	0	0	0
T30	0	401032	0	0
T32	0	41048	0	0
T33	0	216	0	0
T35	0	78776	0	0
T36	0	72	0	0
T37	0	936	0	0
T38	0	69184	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135172308	25987786	0	0
T2	1488	1488	0	0
T3	119518	550744	0	0
T4	728813	41224	0	0
T7	926998	0	0	0
T8	479085	0	0	0
T9	51783	0	0	0
T10	35429	0	0	0
T11	13824	0	0	0
T12	21140	0	0	0
T13	40010	0	0	0
T30	0	401032	0	0
T32	0	41048	0	0
T33	0	216	0	0
T35	0	78776	0	0
T36	0	72	0	0
T37	0	936	0	0
T38	0	69184	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135172308	574802	0	0
T2	1488	171	0	0
T3	119518	6063	0	0
T4	728813	335	0	0
T7	926998	0	0	0
T8	479085	0	0	0
T9	51783	0	0	0
T10	35429	0	0	0
T11	13824	0	0	0
T12	21140	0	0	0
T13	40010	0	0	0
T15	0	6484	0	0
T25	0	5734	0	0
T30	0	5506	0	0
T32	0	1622	0	0
T35	0	3545	0	0
T38	0	2793	0	0
T39	0	2205	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135172308	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135172308	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135172308	574802	0	0
T2	1488	171	0	0
T3	119518	6063	0	0
T4	728813	335	0	0
T7	926998	0	0	0
T8	479085	0	0	0
T9	51783	0	0	0
T10	35429	0	0	0
T11	13824	0	0	0
T12	21140	0	0	0
T13	40010	0	0	0
T15	0	6484	0	0
T25	0	5734	0	0
T30	0	5506	0	0
T32	0	1622	0	0
T35	0	3545	0	0
T38	0	2793	0	0
T39	0	2205	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135172308	574802	0	0
T2	1488	171	0	0
T3	119518	6063	0	0
T4	728813	335	0	0
T7	926998	0	0	0
T8	479085	0	0	0
T9	51783	0	0	0
T10	35429	0	0	0
T11	13824	0	0	0
T12	21140	0	0	0
T13	40010	0	0	0
T15	0	6484	0	0
T25	0	5734	0	0
T30	0	5506	0	0
T32	0	1622	0	0
T35	0	3545	0	0
T38	0	2793	0	0
T39	0	2205	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135172308	574802	0	0
T2	1488	171	0	0
T3	119518	6063	0	0
T4	728813	335	0	0
T7	926998	0	0	0
T8	479085	0	0	0
T9	51783	0	0	0
T10	35429	0	0	0
T11	13824	0	0	0
T12	21140	0	0	0
T13	40010	0	0	0
T15	0	6484	0	0
T25	0	5734	0	0
T30	0	5506	0	0
T32	0	1622	0	0
T35	0	3545	0	0
T38	0	2793	0	0
T39	0	2205	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	135172308	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135172308	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135172308	25987786	0	0
T2	1488	1488	0	0
T3	119518	550744	0	0
T4	728813	41224	0	0
T7	926998	0	0	0
T8	479085	0	0	0
T9	51783	0	0	0
T10	35429	0	0	0
T11	13824	0	0	0
T12	21140	0	0	0
T13	40010	0	0	0
T30	0	401032	0	0
T32	0	41048	0	0
T33	0	216	0	0
T35	0	78776	0	0
T36	0	72	0	0
T37	0	936	0	0
T38	0	69184	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135172308	574802	0	0
T2	1488	171	0	0
T3	119518	6063	0	0
T4	728813	335	0	0
T7	926998	0	0	0
T8	479085	0	0	0
T9	51783	0	0	0
T10	35429	0	0	0
T11	13824	0	0	0
T12	21140	0	0	0
T13	40010	0	0	0
T15	0	6484	0	0
T25	0	5734	0	0
T30	0	5506	0	0
T32	0	1622	0	0
T35	0	3545	0	0
T38	0	2793	0	0
T39	0	2205	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
1	0	Covered	T3,T4,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Unreachable
1	1	Covered	T3,T4,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T7
0	0	1	Unreachable
0	0	0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	135172308	107962890	0	0
CheckNGreaterZero_A	973	973	0	0
GntImpliesReady_A	135172308	690231	0	0
GntImpliesValid_A	135172308	690231	0	0
GrantKnown_A	135172308	107962890	0	0
IdxKnown_A	135172308	107962890	0	0
IndexIsCorrect_A	135172308	690231	0	0
LockArbDecision_A	135172308	0	0	0
NoReadyValidNoGrant_A	135172308	0	0	0
ReadyAndValidImplyGrant_A	135172308	690231	0	0
ReqAndReadyImplyGrant_A	135172308	690231	0	0
ReqImpliesValid_A	135172308	690231	0	0
ReqStaysHighUntilGranted0_M	135172308	0	0	0
RoundRobin_A	135172308	0	0	0
ValidKnown_A	135172308	107962890	0	0
gen_data_port_assertion.DataFlow_A	135172308	690231	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135172308	107962890	0	0
T3	119518	634632	0	0
T4	728813	682573	0	0
T7	926998	923891	0	0
T8	479085	478488	0	0
T9	51783	51496	0	0
T10	35429	35082	0	0
T11	13824	13824	0	0
T12	21140	20840	0	0
T13	40010	39632	0	0
T14	531286	527830	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973	973	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135172308	690231	0	0
T3	119518	1175	0	0
T4	728813	10053	0	0
T7	926998	4198	0	0
T8	479085	2631	0	0
T9	51783	0	0	0
T10	35429	0	0	0
T11	13824	0	0	0
T12	21140	0	0	0
T13	40010	0	0	0
T14	531286	2639	0	0
T32	0	3139	0	0
T49	0	660	0	0
T50	0	4224	0	0
T51	0	2893	0	0
T60	0	1287	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135172308	690231	0	0
T3	119518	1175	0	0
T4	728813	10053	0	0
T7	926998	4198	0	0
T8	479085	2631	0	0
T9	51783	0	0	0
T10	35429	0	0	0
T11	13824	0	0	0
T12	21140	0	0	0
T13	40010	0	0	0
T14	531286	2639	0	0
T32	0	3139	0	0
T49	0	660	0	0
T50	0	4224	0	0
T51	0	2893	0	0
T60	0	1287	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135172308	107962890	0	0
T3	119518	634632	0	0
T4	728813	682573	0	0
T7	926998	923891	0	0
T8	479085	478488	0	0
T9	51783	51496	0	0
T10	35429	35082	0	0
T11	13824	13824	0	0
T12	21140	20840	0	0
T13	40010	39632	0	0
T14	531286	527830	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135172308	107962890	0	0
T3	119518	634632	0	0
T4	728813	682573	0	0
T7	926998	923891	0	0
T8	479085	478488	0	0
T9	51783	51496	0	0
T10	35429	35082	0	0
T11	13824	13824	0	0
T12	21140	20840	0	0
T13	40010	39632	0	0
T14	531286	527830	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135172308	690231	0	0
T3	119518	1175	0	0
T4	728813	10053	0	0
T7	926998	4198	0	0
T8	479085	2631	0	0
T9	51783	0	0	0
T10	35429	0	0	0
T11	13824	0	0	0
T12	21140	0	0	0
T13	40010	0	0	0
T14	531286	2639	0	0
T32	0	3139	0	0
T49	0	660	0	0
T50	0	4224	0	0
T51	0	2893	0	0
T60	0	1287	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135172308	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135172308	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135172308	690231	0	0
T3	119518	1175	0	0
T4	728813	10053	0	0
T7	926998	4198	0	0
T8	479085	2631	0	0
T9	51783	0	0	0
T10	35429	0	0	0
T11	13824	0	0	0
T12	21140	0	0	0
T13	40010	0	0	0
T14	531286	2639	0	0
T32	0	3139	0	0
T49	0	660	0	0
T50	0	4224	0	0
T51	0	2893	0	0
T60	0	1287	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135172308	690231	0	0
T3	119518	1175	0	0
T4	728813	10053	0	0
T7	926998	4198	0	0
T8	479085	2631	0	0
T9	51783	0	0	0
T10	35429	0	0	0
T11	13824	0	0	0
T12	21140	0	0	0
T13	40010	0	0	0
T14	531286	2639	0	0
T32	0	3139	0	0
T49	0	660	0	0
T50	0	4224	0	0
T51	0	2893	0	0
T60	0	1287	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135172308	690231	0	0
T3	119518	1175	0	0
T4	728813	10053	0	0
T7	926998	4198	0	0
T8	479085	2631	0	0
T9	51783	0	0	0
T10	35429	0	0	0
T11	13824	0	0	0
T12	21140	0	0	0
T13	40010	0	0	0
T14	531286	2639	0	0
T32	0	3139	0	0
T49	0	660	0	0
T50	0	4224	0	0
T51	0	2893	0	0
T60	0	1287	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	135172308	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135172308	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135172308	107962890	0	0
T3	119518	634632	0	0
T4	728813	682573	0	0
T7	926998	923891	0	0
T8	479085	478488	0	0
T9	51783	51496	0	0
T10	35429	35082	0	0
T11	13824	13824	0	0
T12	21140	20840	0	0
T13	40010	39632	0	0
T14	531286	527830	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135172308	690231	0	0
T3	119518	1175	0	0
T4	728813	10053	0	0
T7	926998	4198	0	0
T8	479085	2631	0	0
T9	51783	0	0	0
T10	35429	0	0	0
T11	13824	0	0	0
T12	21140	0	0	0
T13	40010	0	0	0
T14	531286	2639	0	0
T32	0	3139	0	0
T49	0	660	0	0
T50	0	4224	0	0
T51	0	2893	0	0
T60	0	1287	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389733150	389644022	0	0
CheckNGreaterZero_A	973	973	0	0
GntImpliesReady_A	389733150	2044594	0	0
GntImpliesValid_A	389733150	2044594	0	0
GrantKnown_A	389733150	389644022	0	0
IdxKnown_A	389733150	389644022	0	0
IndexIsCorrect_A	389733150	2044594	0	0
LockArbDecision_A	389733150	0	0	0
NoReadyValidNoGrant_A	389733150	0	0	0
ReadyAndValidImplyGrant_A	389733150	2044594	0	0
ReqAndReadyImplyGrant_A	389733150	2044594	0	0
ReqImpliesValid_A	389733150	2044594	0	0
ReqStaysHighUntilGranted0_M	389733150	0	0	0
RoundRobin_A	389733150	3	0	973
ValidKnown_A	389733150	389644022	0	0
gen_data_port_assertion.DataFlow_A	389733150	2044594	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389733150	389644022	0	0
T1	798	709	0	0
T2	1488	1390	0	0
T3	404227	404165	0	0
T4	299530	299436	0	0
T5	1632	1582	0	0
T6	1021	962	0	0
T7	289041	289031	0	0
T8	147402	147397	0	0
T9	27246	27156	0	0
T10	25834	25778	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973	973	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389733150	2044594	0	0
T2	1488	43	0	0
T3	404227	10682	0	0
T4	299530	13260	0	0
T5	1632	0	0	0
T6	1021	0	0	0
T7	289041	12023	0	0
T8	147402	4300	0	0
T9	27246	832	0	0
T10	25834	832	0	0
T11	58688	832	0	0
T12	0	832	0	0
T13	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389733150	2044594	0	0
T2	1488	43	0	0
T3	404227	10682	0	0
T4	299530	13260	0	0
T5	1632	0	0	0
T6	1021	0	0	0
T7	289041	12023	0	0
T8	147402	4300	0	0
T9	27246	832	0	0
T10	25834	832	0	0
T11	58688	832	0	0
T12	0	832	0	0
T13	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389733150	389644022	0	0
T1	798	709	0	0
T2	1488	1390	0	0
T3	404227	404165	0	0
T4	299530	299436	0	0
T5	1632	1582	0	0
T6	1021	962	0	0
T7	289041	289031	0	0
T8	147402	147397	0	0
T9	27246	27156	0	0
T10	25834	25778	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389733150	389644022	0	0
T1	798	709	0	0
T2	1488	1390	0	0
T3	404227	404165	0	0
T4	299530	299436	0	0
T5	1632	1582	0	0
T6	1021	962	0	0
T7	289041	289031	0	0
T8	147402	147397	0	0
T9	27246	27156	0	0
T10	25834	25778	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389733150	2044594	0	0
T2	1488	43	0	0
T3	404227	10682	0	0
T4	299530	13260	0	0
T5	1632	0	0	0
T6	1021	0	0	0
T7	289041	12023	0	0
T8	147402	4300	0	0
T9	27246	832	0	0
T10	25834	832	0	0
T11	58688	832	0	0
T12	0	832	0	0
T13	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389733150	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389733150	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389733150	2044594	0	0
T2	1488	43	0	0
T3	404227	10682	0	0
T4	299530	13260	0	0
T5	1632	0	0	0
T6	1021	0	0	0
T7	289041	12023	0	0
T8	147402	4300	0	0
T9	27246	832	0	0
T10	25834	832	0	0
T11	58688	832	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389733150	2044594	0	0
T2	1488	43	0	0
T3	404227	10682	0	0
T4	299530	13260	0	0
T5	1632	0	0	0
T6	1021	0	0	0
T7	289041	12023	0	0
T8	147402	4300	0	0
T9	27246	832	0	0
T10	25834	832	0	0
T11	58688	832	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389733150	2044594	0	0
T2	1488	43	0	0
T3	404227	10682	0	0
T4	299530	13260	0	0
T5	1632	0	0	0
T6	1021	0	0	0
T7	289041	12023	0	0
T8	147402	4300	0	0
T9	27246	832	0	0
T10	25834	832	0	0
T11	58688	832	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389733150	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389733150	3	0	973
T3	404227	1	0	1
T4	299530	0	0	1
T5	1632	0	0	1
T6	1021	0	0	1
T7	289041	0	0	1
T8	147402	0	0	1
T9	27246	0	0	1
T10	25834	0	0	1
T11	58688	0	0	1
T12	18739	0	0	1
T58	0	1	0	0
T59	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389733150	389644022	0	0
T1	798	709	0	0
T2	1488	1390	0	0
T3	404227	404165	0	0
T4	299530	299436	0	0
T5	1632	1582	0	0
T6	1021	962	0	0
T7	289041	289031	0	0
T8	147402	147397	0	0
T9	27246	27156	0	0
T10	25834	25778	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389733150	2044594	0	0
T2	1488	43	0	0
T3	404227	10682	0	0
T4	299530	13260	0	0
T5	1632	0	0	0
T6	1021	0	0	0
T7	289041	12023	0	0
T8	147402	4300	0	0
T9	27246	832	0	0
T10	25834	832	0	0
T11	58688	832	0	0
T12	0	832	0	0
T13	0	832	0	0