Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
3525 |
0 |
0 |
T90 |
55563 |
1 |
0 |
0 |
T91 |
3964 |
189 |
0 |
0 |
T93 |
16682 |
128 |
0 |
0 |
T94 |
5396 |
1 |
0 |
0 |
T96 |
3668 |
12 |
0 |
0 |
T97 |
4133 |
83 |
0 |
0 |
T98 |
7196 |
267 |
0 |
0 |
T102 |
16716 |
203 |
0 |
0 |
T110 |
10712 |
2 |
0 |
0 |
T111 |
2298 |
77 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
1605 |
0 |
0 |
T92 |
29974 |
33 |
0 |
0 |
T94 |
5396 |
6 |
0 |
0 |
T110 |
10712 |
15 |
0 |
0 |
T115 |
269853 |
627 |
0 |
0 |
T121 |
3922 |
3 |
0 |
0 |
T140 |
18494 |
3 |
0 |
0 |
T154 |
4394 |
1 |
0 |
0 |
T155 |
10681 |
8 |
0 |
0 |
T156 |
21086 |
97 |
0 |
0 |
T157 |
21283 |
53 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
1594 |
0 |
0 |
T92 |
29974 |
28 |
0 |
0 |
T94 |
5396 |
4 |
0 |
0 |
T110 |
10712 |
20 |
0 |
0 |
T115 |
269853 |
661 |
0 |
0 |
T122 |
8599 |
4 |
0 |
0 |
T140 |
18494 |
36 |
0 |
0 |
T154 |
4394 |
4 |
0 |
0 |
T155 |
10681 |
21 |
0 |
0 |
T156 |
21086 |
65 |
0 |
0 |
T157 |
21283 |
64 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
2086 |
0 |
0 |
T92 |
29974 |
42 |
0 |
0 |
T94 |
5396 |
5 |
0 |
0 |
T110 |
10712 |
42 |
0 |
0 |
T115 |
269853 |
636 |
0 |
0 |
T122 |
8599 |
12 |
0 |
0 |
T140 |
18494 |
50 |
0 |
0 |
T154 |
4394 |
16 |
0 |
0 |
T155 |
10681 |
30 |
0 |
0 |
T156 |
21086 |
47 |
0 |
0 |
T157 |
21283 |
35 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
7807 |
0 |
0 |
T92 |
29974 |
456 |
0 |
0 |
T94 |
5396 |
8 |
0 |
0 |
T110 |
10712 |
21 |
0 |
0 |
T115 |
269853 |
686 |
0 |
0 |
T121 |
3922 |
94 |
0 |
0 |
T122 |
8599 |
3 |
0 |
0 |
T140 |
18494 |
15 |
0 |
0 |
T154 |
4394 |
5 |
0 |
0 |
T155 |
10681 |
14 |
0 |
0 |
T156 |
21086 |
66 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
8247 |
0 |
0 |
T92 |
29974 |
380 |
0 |
0 |
T94 |
5396 |
10 |
0 |
0 |
T110 |
10712 |
131 |
0 |
0 |
T115 |
269853 |
699 |
0 |
0 |
T121 |
3922 |
4 |
0 |
0 |
T122 |
8599 |
78 |
0 |
0 |
T140 |
18494 |
28 |
0 |
0 |
T154 |
4394 |
5 |
0 |
0 |
T155 |
10681 |
274 |
0 |
0 |
T156 |
21086 |
73 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
7962 |
0 |
0 |
T92 |
29974 |
60 |
0 |
0 |
T94 |
5396 |
52 |
0 |
0 |
T110 |
10712 |
265 |
0 |
0 |
T115 |
269853 |
704 |
0 |
0 |
T121 |
3922 |
6 |
0 |
0 |
T122 |
8599 |
190 |
0 |
0 |
T140 |
18494 |
32 |
0 |
0 |
T154 |
4394 |
137 |
0 |
0 |
T155 |
10681 |
146 |
0 |
0 |
T156 |
21086 |
68 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
8919 |
0 |
0 |
T92 |
29974 |
146 |
0 |
0 |
T110 |
10712 |
264 |
0 |
0 |
T115 |
269853 |
677 |
0 |
0 |
T121 |
3922 |
127 |
0 |
0 |
T122 |
8599 |
58 |
0 |
0 |
T140 |
18494 |
23 |
0 |
0 |
T154 |
4394 |
143 |
0 |
0 |
T155 |
10681 |
117 |
0 |
0 |
T156 |
21086 |
116 |
0 |
0 |
T157 |
21283 |
30 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
8586 |
0 |
0 |
T92 |
29974 |
417 |
0 |
0 |
T94 |
5396 |
73 |
0 |
0 |
T110 |
10712 |
251 |
0 |
0 |
T115 |
269853 |
726 |
0 |
0 |
T121 |
3922 |
96 |
0 |
0 |
T122 |
8599 |
93 |
0 |
0 |
T140 |
18494 |
16 |
0 |
0 |
T154 |
4394 |
6 |
0 |
0 |
T155 |
10681 |
220 |
0 |
0 |
T156 |
21086 |
82 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
8139 |
0 |
0 |
T92 |
29974 |
337 |
0 |
0 |
T94 |
5396 |
19 |
0 |
0 |
T110 |
10712 |
145 |
0 |
0 |
T115 |
269853 |
739 |
0 |
0 |
T121 |
3922 |
137 |
0 |
0 |
T122 |
8599 |
14 |
0 |
0 |
T140 |
18494 |
19 |
0 |
0 |
T155 |
10681 |
244 |
0 |
0 |
T156 |
21086 |
76 |
0 |
0 |
T157 |
21283 |
39 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
9720 |
0 |
0 |
T92 |
29974 |
367 |
0 |
0 |
T94 |
5396 |
69 |
0 |
0 |
T110 |
10712 |
102 |
0 |
0 |
T115 |
269853 |
699 |
0 |
0 |
T121 |
3922 |
88 |
0 |
0 |
T122 |
8599 |
152 |
0 |
0 |
T140 |
18494 |
30 |
0 |
0 |
T154 |
4394 |
7 |
0 |
0 |
T155 |
10681 |
278 |
0 |
0 |
T156 |
21086 |
82 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
9066 |
0 |
0 |
T92 |
29974 |
313 |
0 |
0 |
T94 |
5396 |
48 |
0 |
0 |
T110 |
10712 |
274 |
0 |
0 |
T115 |
269853 |
772 |
0 |
0 |
T121 |
3922 |
89 |
0 |
0 |
T122 |
8599 |
3 |
0 |
0 |
T140 |
18494 |
56 |
0 |
0 |
T154 |
4394 |
106 |
0 |
0 |
T155 |
10681 |
181 |
0 |
0 |
T156 |
21086 |
48 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
4355 |
0 |
0 |
T92 |
29974 |
224 |
0 |
0 |
T94 |
5396 |
12 |
0 |
0 |
T110 |
10712 |
11 |
0 |
0 |
T115 |
269853 |
726 |
0 |
0 |
T122 |
8599 |
27 |
0 |
0 |
T140 |
18494 |
38 |
0 |
0 |
T154 |
4394 |
10 |
0 |
0 |
T155 |
10681 |
16 |
0 |
0 |
T156 |
21086 |
49 |
0 |
0 |
T157 |
21283 |
63 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
4268 |
0 |
0 |
T92 |
29974 |
93 |
0 |
0 |
T94 |
5396 |
10 |
0 |
0 |
T110 |
10712 |
74 |
0 |
0 |
T115 |
269853 |
614 |
0 |
0 |
T121 |
3922 |
4 |
0 |
0 |
T122 |
8599 |
41 |
0 |
0 |
T140 |
18494 |
55 |
0 |
0 |
T154 |
4394 |
45 |
0 |
0 |
T155 |
10681 |
54 |
0 |
0 |
T156 |
21086 |
68 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
3730 |
0 |
0 |
T92 |
29974 |
152 |
0 |
0 |
T94 |
5396 |
22 |
0 |
0 |
T110 |
10712 |
19 |
0 |
0 |
T115 |
269853 |
659 |
0 |
0 |
T121 |
3922 |
5 |
0 |
0 |
T122 |
8599 |
10 |
0 |
0 |
T140 |
18494 |
32 |
0 |
0 |
T154 |
4394 |
5 |
0 |
0 |
T155 |
10681 |
19 |
0 |
0 |
T156 |
21086 |
79 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
4193 |
0 |
0 |
T92 |
29974 |
171 |
0 |
0 |
T94 |
5396 |
4 |
0 |
0 |
T110 |
10712 |
73 |
0 |
0 |
T115 |
269853 |
639 |
0 |
0 |
T121 |
3922 |
6 |
0 |
0 |
T122 |
8599 |
29 |
0 |
0 |
T140 |
18494 |
49 |
0 |
0 |
T154 |
4394 |
3 |
0 |
0 |
T155 |
10681 |
58 |
0 |
0 |
T156 |
21086 |
84 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
4409 |
0 |
0 |
T92 |
29974 |
121 |
0 |
0 |
T94 |
5396 |
3 |
0 |
0 |
T110 |
10712 |
62 |
0 |
0 |
T115 |
269853 |
665 |
0 |
0 |
T121 |
3922 |
36 |
0 |
0 |
T122 |
8599 |
26 |
0 |
0 |
T140 |
18494 |
46 |
0 |
0 |
T154 |
4394 |
51 |
0 |
0 |
T155 |
10681 |
43 |
0 |
0 |
T156 |
21086 |
50 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
4493 |
0 |
0 |
T92 |
29974 |
109 |
0 |
0 |
T94 |
5396 |
3 |
0 |
0 |
T110 |
10712 |
133 |
0 |
0 |
T115 |
269853 |
694 |
0 |
0 |
T121 |
3922 |
6 |
0 |
0 |
T122 |
8599 |
42 |
0 |
0 |
T140 |
18494 |
29 |
0 |
0 |
T154 |
4394 |
7 |
0 |
0 |
T155 |
10681 |
57 |
0 |
0 |
T156 |
21086 |
98 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
4215 |
0 |
0 |
T92 |
29974 |
158 |
0 |
0 |
T110 |
10712 |
115 |
0 |
0 |
T115 |
269853 |
697 |
0 |
0 |
T121 |
3922 |
43 |
0 |
0 |
T122 |
8599 |
37 |
0 |
0 |
T140 |
18494 |
16 |
0 |
0 |
T154 |
4394 |
54 |
0 |
0 |
T155 |
10681 |
54 |
0 |
0 |
T156 |
21086 |
37 |
0 |
0 |
T157 |
21283 |
99 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
4095 |
0 |
0 |
T92 |
29974 |
144 |
0 |
0 |
T94 |
5396 |
6 |
0 |
0 |
T110 |
10712 |
66 |
0 |
0 |
T115 |
269853 |
616 |
0 |
0 |
T121 |
3922 |
36 |
0 |
0 |
T122 |
8599 |
41 |
0 |
0 |
T140 |
18494 |
33 |
0 |
0 |
T154 |
4394 |
1 |
0 |
0 |
T155 |
10681 |
17 |
0 |
0 |
T156 |
21086 |
50 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
4137 |
0 |
0 |
T92 |
29974 |
198 |
0 |
0 |
T94 |
5396 |
26 |
0 |
0 |
T110 |
10712 |
57 |
0 |
0 |
T115 |
269853 |
651 |
0 |
0 |
T121 |
3922 |
52 |
0 |
0 |
T122 |
8599 |
20 |
0 |
0 |
T140 |
18494 |
21 |
0 |
0 |
T154 |
4394 |
72 |
0 |
0 |
T155 |
10681 |
88 |
0 |
0 |
T156 |
21086 |
70 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
4320 |
0 |
0 |
T92 |
29974 |
140 |
0 |
0 |
T110 |
10712 |
9 |
0 |
0 |
T115 |
269853 |
684 |
0 |
0 |
T122 |
8599 |
46 |
0 |
0 |
T140 |
18494 |
32 |
0 |
0 |
T154 |
4394 |
49 |
0 |
0 |
T155 |
10681 |
67 |
0 |
0 |
T156 |
21086 |
104 |
0 |
0 |
T157 |
21283 |
76 |
0 |
0 |
T158 |
5554 |
1 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
4472 |
0 |
0 |
T92 |
29974 |
101 |
0 |
0 |
T94 |
5396 |
15 |
0 |
0 |
T110 |
10712 |
16 |
0 |
0 |
T115 |
269853 |
644 |
0 |
0 |
T121 |
3922 |
52 |
0 |
0 |
T122 |
8599 |
61 |
0 |
0 |
T140 |
18494 |
18 |
0 |
0 |
T154 |
4394 |
49 |
0 |
0 |
T155 |
10681 |
53 |
0 |
0 |
T156 |
21086 |
93 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
4164 |
0 |
0 |
T92 |
29974 |
123 |
0 |
0 |
T94 |
5396 |
29 |
0 |
0 |
T110 |
10712 |
50 |
0 |
0 |
T115 |
269853 |
743 |
0 |
0 |
T122 |
8599 |
51 |
0 |
0 |
T140 |
18494 |
16 |
0 |
0 |
T154 |
4394 |
4 |
0 |
0 |
T155 |
10681 |
13 |
0 |
0 |
T156 |
21086 |
87 |
0 |
0 |
T157 |
21283 |
57 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
4394 |
0 |
0 |
T92 |
29974 |
45 |
0 |
0 |
T94 |
5396 |
27 |
0 |
0 |
T110 |
10712 |
95 |
0 |
0 |
T115 |
269853 |
605 |
0 |
0 |
T121 |
3922 |
47 |
0 |
0 |
T122 |
8599 |
67 |
0 |
0 |
T140 |
18494 |
57 |
0 |
0 |
T154 |
4394 |
27 |
0 |
0 |
T155 |
10681 |
62 |
0 |
0 |
T156 |
21086 |
28 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
3911 |
0 |
0 |
T92 |
29974 |
146 |
0 |
0 |
T94 |
5396 |
21 |
0 |
0 |
T110 |
10712 |
55 |
0 |
0 |
T115 |
269853 |
654 |
0 |
0 |
T121 |
3922 |
4 |
0 |
0 |
T122 |
8599 |
37 |
0 |
0 |
T140 |
18494 |
65 |
0 |
0 |
T154 |
4394 |
1 |
0 |
0 |
T155 |
10681 |
17 |
0 |
0 |
T156 |
21086 |
59 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
4570 |
0 |
0 |
T92 |
29974 |
115 |
0 |
0 |
T94 |
5396 |
43 |
0 |
0 |
T110 |
10712 |
76 |
0 |
0 |
T115 |
269853 |
609 |
0 |
0 |
T121 |
3922 |
8 |
0 |
0 |
T122 |
8599 |
33 |
0 |
0 |
T140 |
18494 |
40 |
0 |
0 |
T154 |
4394 |
2 |
0 |
0 |
T155 |
10681 |
114 |
0 |
0 |
T156 |
21086 |
69 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
4390 |
0 |
0 |
T92 |
29974 |
96 |
0 |
0 |
T110 |
10712 |
8 |
0 |
0 |
T115 |
269853 |
674 |
0 |
0 |
T121 |
3922 |
3 |
0 |
0 |
T122 |
8599 |
38 |
0 |
0 |
T140 |
18494 |
4 |
0 |
0 |
T154 |
4394 |
62 |
0 |
0 |
T155 |
10681 |
95 |
0 |
0 |
T156 |
21086 |
93 |
0 |
0 |
T157 |
21283 |
25 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
4367 |
0 |
0 |
T92 |
29974 |
80 |
0 |
0 |
T94 |
5396 |
13 |
0 |
0 |
T110 |
10712 |
76 |
0 |
0 |
T115 |
269853 |
677 |
0 |
0 |
T121 |
3922 |
44 |
0 |
0 |
T122 |
8599 |
35 |
0 |
0 |
T140 |
18494 |
20 |
0 |
0 |
T154 |
4394 |
37 |
0 |
0 |
T155 |
10681 |
92 |
0 |
0 |
T156 |
21086 |
20 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
4118 |
0 |
0 |
T92 |
29974 |
210 |
0 |
0 |
T94 |
5396 |
26 |
0 |
0 |
T110 |
10712 |
22 |
0 |
0 |
T115 |
269853 |
676 |
0 |
0 |
T121 |
3922 |
5 |
0 |
0 |
T122 |
8599 |
34 |
0 |
0 |
T140 |
18494 |
24 |
0 |
0 |
T154 |
4394 |
50 |
0 |
0 |
T155 |
10681 |
20 |
0 |
0 |
T156 |
21086 |
29 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
4181 |
0 |
0 |
T92 |
29974 |
126 |
0 |
0 |
T94 |
5396 |
42 |
0 |
0 |
T110 |
10712 |
76 |
0 |
0 |
T115 |
269853 |
663 |
0 |
0 |
T121 |
3922 |
5 |
0 |
0 |
T122 |
8599 |
20 |
0 |
0 |
T140 |
18494 |
54 |
0 |
0 |
T154 |
4394 |
52 |
0 |
0 |
T155 |
10681 |
21 |
0 |
0 |
T156 |
21086 |
63 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
4346 |
0 |
0 |
T92 |
29974 |
107 |
0 |
0 |
T94 |
5396 |
7 |
0 |
0 |
T110 |
10712 |
105 |
0 |
0 |
T115 |
269853 |
651 |
0 |
0 |
T121 |
3922 |
4 |
0 |
0 |
T122 |
8599 |
56 |
0 |
0 |
T140 |
18494 |
14 |
0 |
0 |
T154 |
4394 |
41 |
0 |
0 |
T155 |
10681 |
81 |
0 |
0 |
T156 |
21086 |
90 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
4110 |
0 |
0 |
T92 |
29974 |
136 |
0 |
0 |
T110 |
10712 |
86 |
0 |
0 |
T115 |
269853 |
676 |
0 |
0 |
T122 |
8599 |
7 |
0 |
0 |
T140 |
18494 |
12 |
0 |
0 |
T154 |
4394 |
58 |
0 |
0 |
T155 |
10681 |
26 |
0 |
0 |
T156 |
21086 |
80 |
0 |
0 |
T157 |
21283 |
59 |
0 |
0 |
T158 |
5554 |
40 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
4403 |
0 |
0 |
T92 |
29974 |
88 |
0 |
0 |
T110 |
10712 |
72 |
0 |
0 |
T115 |
269853 |
685 |
0 |
0 |
T121 |
3922 |
6 |
0 |
0 |
T122 |
8599 |
45 |
0 |
0 |
T140 |
18494 |
23 |
0 |
0 |
T154 |
4394 |
42 |
0 |
0 |
T155 |
10681 |
69 |
0 |
0 |
T156 |
21086 |
63 |
0 |
0 |
T157 |
21283 |
37 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
4136 |
0 |
0 |
T92 |
29974 |
142 |
0 |
0 |
T94 |
5396 |
8 |
0 |
0 |
T110 |
10712 |
7 |
0 |
0 |
T115 |
269853 |
696 |
0 |
0 |
T122 |
8599 |
15 |
0 |
0 |
T140 |
18494 |
32 |
0 |
0 |
T154 |
4394 |
3 |
0 |
0 |
T155 |
10681 |
84 |
0 |
0 |
T156 |
21086 |
55 |
0 |
0 |
T157 |
21283 |
52 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
4024 |
0 |
0 |
T92 |
29974 |
70 |
0 |
0 |
T94 |
5396 |
33 |
0 |
0 |
T110 |
10712 |
49 |
0 |
0 |
T115 |
269853 |
653 |
0 |
0 |
T121 |
3922 |
33 |
0 |
0 |
T122 |
8599 |
41 |
0 |
0 |
T140 |
18494 |
29 |
0 |
0 |
T154 |
4394 |
1 |
0 |
0 |
T155 |
10681 |
51 |
0 |
0 |
T156 |
21086 |
28 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
1941 |
0 |
0 |
T92 |
29974 |
14 |
0 |
0 |
T110 |
10712 |
22 |
0 |
0 |
T115 |
269853 |
659 |
0 |
0 |
T121 |
3922 |
5 |
0 |
0 |
T122 |
8599 |
22 |
0 |
0 |
T140 |
18494 |
40 |
0 |
0 |
T154 |
4394 |
7 |
0 |
0 |
T155 |
10681 |
22 |
0 |
0 |
T156 |
21086 |
86 |
0 |
0 |
T157 |
21283 |
73 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
1860 |
0 |
0 |
T92 |
29974 |
33 |
0 |
0 |
T110 |
10712 |
14 |
0 |
0 |
T115 |
269853 |
635 |
0 |
0 |
T121 |
3922 |
7 |
0 |
0 |
T122 |
8599 |
5 |
0 |
0 |
T140 |
18494 |
32 |
0 |
0 |
T154 |
4394 |
7 |
0 |
0 |
T155 |
10681 |
19 |
0 |
0 |
T156 |
21086 |
78 |
0 |
0 |
T157 |
21283 |
78 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
1917 |
0 |
0 |
T92 |
29974 |
34 |
0 |
0 |
T94 |
5396 |
2 |
0 |
0 |
T110 |
10712 |
33 |
0 |
0 |
T115 |
269853 |
682 |
0 |
0 |
T121 |
3922 |
5 |
0 |
0 |
T122 |
8599 |
27 |
0 |
0 |
T140 |
18494 |
33 |
0 |
0 |
T154 |
4394 |
5 |
0 |
0 |
T155 |
10681 |
22 |
0 |
0 |
T156 |
21086 |
105 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
1885 |
0 |
0 |
T92 |
29974 |
17 |
0 |
0 |
T94 |
5396 |
11 |
0 |
0 |
T110 |
10712 |
12 |
0 |
0 |
T115 |
269853 |
676 |
0 |
0 |
T121 |
3922 |
14 |
0 |
0 |
T122 |
8599 |
9 |
0 |
0 |
T140 |
18494 |
56 |
0 |
0 |
T154 |
4394 |
6 |
0 |
0 |
T155 |
10681 |
18 |
0 |
0 |
T156 |
21086 |
50 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
2501 |
0 |
0 |
T92 |
29974 |
79 |
0 |
0 |
T94 |
5396 |
1 |
0 |
0 |
T110 |
10712 |
12 |
0 |
0 |
T115 |
269853 |
761 |
0 |
0 |
T121 |
3922 |
17 |
0 |
0 |
T122 |
8599 |
12 |
0 |
0 |
T140 |
18494 |
42 |
0 |
0 |
T154 |
4394 |
5 |
0 |
0 |
T155 |
10681 |
31 |
0 |
0 |
T156 |
21086 |
30 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
4215 |
0 |
0 |
T15 |
264196 |
3 |
0 |
0 |
T16 |
5504 |
28 |
0 |
0 |
T18 |
0 |
31 |
0 |
0 |
T20 |
0 |
41 |
0 |
0 |
T24 |
45183 |
0 |
0 |
0 |
T25 |
136567 |
0 |
0 |
0 |
T26 |
515697 |
0 |
0 |
0 |
T27 |
206205 |
0 |
0 |
0 |
T28 |
813712 |
0 |
0 |
0 |
T29 |
97666 |
0 |
0 |
0 |
T41 |
207431 |
0 |
0 |
0 |
T42 |
1348 |
0 |
0 |
0 |
T159 |
0 |
14 |
0 |
0 |
T160 |
0 |
54 |
0 |
0 |
T161 |
0 |
46 |
0 |
0 |
T162 |
0 |
10 |
0 |
0 |
T163 |
0 |
10 |
0 |
0 |
T164 |
0 |
14 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
1754 |
0 |
0 |
T92 |
29974 |
48 |
0 |
0 |
T94 |
5396 |
2 |
0 |
0 |
T110 |
10712 |
17 |
0 |
0 |
T115 |
269853 |
636 |
0 |
0 |
T121 |
3922 |
2 |
0 |
0 |
T122 |
8599 |
5 |
0 |
0 |
T140 |
18494 |
53 |
0 |
0 |
T154 |
4394 |
1 |
0 |
0 |
T155 |
10681 |
17 |
0 |
0 |
T156 |
21086 |
91 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
2093 |
0 |
0 |
T92 |
29974 |
30 |
0 |
0 |
T94 |
5396 |
5 |
0 |
0 |
T110 |
10712 |
31 |
0 |
0 |
T115 |
269853 |
655 |
0 |
0 |
T121 |
3922 |
3 |
0 |
0 |
T122 |
8599 |
16 |
0 |
0 |
T140 |
18494 |
47 |
0 |
0 |
T154 |
4394 |
13 |
0 |
0 |
T155 |
10681 |
24 |
0 |
0 |
T156 |
21086 |
101 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
1624 |
0 |
0 |
T92 |
29974 |
43 |
0 |
0 |
T110 |
10712 |
13 |
0 |
0 |
T115 |
269853 |
640 |
0 |
0 |
T121 |
3922 |
1 |
0 |
0 |
T122 |
8599 |
7 |
0 |
0 |
T140 |
18494 |
33 |
0 |
0 |
T154 |
4394 |
2 |
0 |
0 |
T155 |
10681 |
26 |
0 |
0 |
T156 |
21086 |
33 |
0 |
0 |
T157 |
21283 |
113 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
1736 |
0 |
0 |
T92 |
29974 |
11 |
0 |
0 |
T94 |
5396 |
3 |
0 |
0 |
T110 |
10712 |
30 |
0 |
0 |
T115 |
269853 |
756 |
0 |
0 |
T121 |
3922 |
2 |
0 |
0 |
T122 |
8599 |
12 |
0 |
0 |
T140 |
18494 |
45 |
0 |
0 |
T154 |
4394 |
1 |
0 |
0 |
T155 |
10681 |
17 |
0 |
0 |
T156 |
21086 |
44 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
1633 |
0 |
0 |
T92 |
29974 |
20 |
0 |
0 |
T94 |
5396 |
2 |
0 |
0 |
T110 |
10712 |
18 |
0 |
0 |
T115 |
269853 |
729 |
0 |
0 |
T121 |
3922 |
3 |
0 |
0 |
T122 |
8599 |
4 |
0 |
0 |
T140 |
18494 |
34 |
0 |
0 |
T154 |
4394 |
6 |
0 |
0 |
T155 |
10681 |
12 |
0 |
0 |
T156 |
21086 |
30 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
1672 |
0 |
0 |
T92 |
29974 |
32 |
0 |
0 |
T110 |
10712 |
14 |
0 |
0 |
T115 |
269853 |
680 |
0 |
0 |
T121 |
3922 |
5 |
0 |
0 |
T122 |
8599 |
10 |
0 |
0 |
T140 |
18494 |
39 |
0 |
0 |
T154 |
4394 |
1 |
0 |
0 |
T155 |
10681 |
22 |
0 |
0 |
T156 |
21086 |
69 |
0 |
0 |
T157 |
21283 |
58 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
2317 |
0 |
0 |
T92 |
29974 |
40 |
0 |
0 |
T110 |
10712 |
19 |
0 |
0 |
T115 |
269853 |
689 |
0 |
0 |
T122 |
8599 |
30 |
0 |
0 |
T140 |
18494 |
20 |
0 |
0 |
T154 |
4394 |
4 |
0 |
0 |
T155 |
10681 |
16 |
0 |
0 |
T156 |
21086 |
29 |
0 |
0 |
T157 |
21283 |
120 |
0 |
0 |
T158 |
5554 |
6 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
1671 |
0 |
0 |
T92 |
29974 |
24 |
0 |
0 |
T94 |
5396 |
4 |
0 |
0 |
T110 |
10712 |
30 |
0 |
0 |
T115 |
269853 |
629 |
0 |
0 |
T122 |
8599 |
1 |
0 |
0 |
T140 |
18494 |
39 |
0 |
0 |
T154 |
4394 |
1 |
0 |
0 |
T155 |
10681 |
17 |
0 |
0 |
T156 |
21086 |
58 |
0 |
0 |
T157 |
21283 |
91 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
2449 |
0 |
0 |
T92 |
29974 |
50 |
0 |
0 |
T94 |
5396 |
1 |
0 |
0 |
T110 |
10712 |
8 |
0 |
0 |
T115 |
269853 |
713 |
0 |
0 |
T121 |
3922 |
8 |
0 |
0 |
T122 |
8599 |
27 |
0 |
0 |
T140 |
18494 |
43 |
0 |
0 |
T154 |
4394 |
10 |
0 |
0 |
T155 |
10681 |
55 |
0 |
0 |
T156 |
21086 |
105 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
1829 |
0 |
0 |
T110 |
10712 |
24 |
0 |
0 |
T115 |
269853 |
663 |
0 |
0 |
T121 |
3922 |
5 |
0 |
0 |
T140 |
18494 |
13 |
0 |
0 |
T154 |
4394 |
3 |
0 |
0 |
T155 |
10681 |
9 |
0 |
0 |
T156 |
21086 |
101 |
0 |
0 |
T157 |
21283 |
18 |
0 |
0 |
T158 |
5554 |
16 |
0 |
0 |
T165 |
16735 |
27 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
1623 |
0 |
0 |
T92 |
29974 |
22 |
0 |
0 |
T94 |
5396 |
3 |
0 |
0 |
T110 |
10712 |
14 |
0 |
0 |
T115 |
269853 |
689 |
0 |
0 |
T121 |
3922 |
4 |
0 |
0 |
T122 |
8599 |
7 |
0 |
0 |
T140 |
18494 |
18 |
0 |
0 |
T154 |
4394 |
4 |
0 |
0 |
T155 |
10681 |
22 |
0 |
0 |
T156 |
21086 |
35 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
1534 |
0 |
0 |
T92 |
29974 |
14 |
0 |
0 |
T94 |
5396 |
6 |
0 |
0 |
T110 |
10712 |
16 |
0 |
0 |
T115 |
269853 |
621 |
0 |
0 |
T121 |
3922 |
2 |
0 |
0 |
T122 |
8599 |
7 |
0 |
0 |
T140 |
18494 |
35 |
0 |
0 |
T154 |
4394 |
2 |
0 |
0 |
T155 |
10681 |
18 |
0 |
0 |
T156 |
21086 |
70 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
1672 |
0 |
0 |
T92 |
29974 |
19 |
0 |
0 |
T94 |
5396 |
9 |
0 |
0 |
T110 |
10712 |
20 |
0 |
0 |
T115 |
269853 |
728 |
0 |
0 |
T121 |
3922 |
2 |
0 |
0 |
T122 |
8599 |
6 |
0 |
0 |
T140 |
18494 |
25 |
0 |
0 |
T154 |
4394 |
4 |
0 |
0 |
T155 |
10681 |
13 |
0 |
0 |
T156 |
21086 |
53 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
1565 |
0 |
0 |
T92 |
29974 |
22 |
0 |
0 |
T94 |
5396 |
2 |
0 |
0 |
T110 |
10712 |
7 |
0 |
0 |
T115 |
269853 |
683 |
0 |
0 |
T122 |
8599 |
2 |
0 |
0 |
T140 |
18494 |
20 |
0 |
0 |
T154 |
4394 |
2 |
0 |
0 |
T155 |
10681 |
20 |
0 |
0 |
T156 |
21086 |
50 |
0 |
0 |
T157 |
21283 |
65 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
1593 |
0 |
0 |
T92 |
29974 |
10 |
0 |
0 |
T94 |
5396 |
6 |
0 |
0 |
T110 |
10712 |
15 |
0 |
0 |
T115 |
269853 |
656 |
0 |
0 |
T121 |
3922 |
1 |
0 |
0 |
T122 |
8599 |
1 |
0 |
0 |
T140 |
18494 |
23 |
0 |
0 |
T155 |
10681 |
11 |
0 |
0 |
T156 |
21086 |
87 |
0 |
0 |
T157 |
21283 |
57 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
392124215 |
1700 |
0 |
0 |
T92 |
29974 |
23 |
0 |
0 |
T110 |
10712 |
17 |
0 |
0 |
T115 |
269853 |
685 |
0 |
0 |
T121 |
3922 |
1 |
0 |
0 |
T122 |
8599 |
7 |
0 |
0 |
T140 |
18494 |
31 |
0 |
0 |
T154 |
4394 |
4 |
0 |
0 |
T155 |
10681 |
13 |
0 |
0 |
T156 |
21086 |
58 |
0 |
0 |
T157 |
21283 |
81 |
0 |
0 |