Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3803103	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4355581

1

T1

1604

T2

59

T3

11098

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4622996	1			T1	1408		T2	235		T3	2697
values[0x0]	1767534	1			T1	474		T2	24		T3	4798
values[0x1]	1768154	1			T1	417		T2	31		T3	4891

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2704258	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5454426

1

T1

1747

T2

134

T3

11354

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	35169	1			T1	11		T2	1		T3	72
valid_sources[0x01]	30656	1			T1	14		T3	25		T4	143
valid_sources[0x02]	30415	1			T1	14		T3	41		T4	158
valid_sources[0x03]	31434	1			T1	5		T2	3		T3	63
valid_sources[0x04]	68691	1			T1	14		T3	31		T4	152
valid_sources[0x05]	29292	1			T1	4		T2	1		T3	36
valid_sources[0x06]	51244	1			T1	18		T2	1		T3	56
valid_sources[0x07]	29385	1			T1	3		T2	2		T3	77
valid_sources[0x08]	29034	1			T1	7		T2	1		T3	42
valid_sources[0x09]	30694	1			T1	9		T2	1		T3	67
valid_sources[0x0a]	31315	1			T1	4		T3	49		T4	172
valid_sources[0x0b]	29258	1			T1	2		T2	1		T3	32
valid_sources[0x0c]	28219	1			T1	2		T2	1		T3	96
valid_sources[0x0d]	31840	1			T1	8		T3	17		T4	137
valid_sources[0x0e]	31011	1			T1	6		T2	2		T3	46
valid_sources[0x0f]	30246	1			T1	27		T3	28		T4	138
valid_sources[0x10]	28002	1			T1	17		T3	56		T4	144
valid_sources[0x11]	30528	1			T1	4		T3	47		T4	161
valid_sources[0x12]	29702	1			T1	5		T2	3		T3	63
valid_sources[0x13]	30282	1			T1	2		T2	1		T3	71
valid_sources[0x14]	28458	1			T1	4		T3	26		T4	165
valid_sources[0x15]	29124	1			T1	6		T2	1		T3	25
valid_sources[0x16]	27954	1			T1	3		T3	39		T4	125
valid_sources[0x17]	36135	1			T1	8		T2	1		T3	31
valid_sources[0x18]	29877	1			T1	3		T2	4		T3	44
valid_sources[0x19]	30769	1			T1	1		T2	2		T3	45
valid_sources[0x1a]	29306	1			T1	11		T2	1		T3	53
valid_sources[0x1b]	28781	1			T1	3		T2	2		T3	49
valid_sources[0x1c]	27984	1			T1	9		T2	2		T3	46
valid_sources[0x1d]	30088	1			T1	24		T2	2		T3	43
valid_sources[0x1e]	28348	1			T1	25		T3	69		T4	139
valid_sources[0x1f]	36726	1			T1	4		T2	3		T3	72
valid_sources[0x20]	29548	1			T1	11		T2	1		T3	70
valid_sources[0x21]	29934	1			T1	4		T2	1		T3	53
valid_sources[0x22]	33249	1			T1	2		T3	64		T4	128
valid_sources[0x23]	28775	1			T1	7		T2	1		T3	54
valid_sources[0x24]	29935	1			T1	10		T3	46		T4	148
valid_sources[0x25]	29137	1			T1	14		T2	1		T3	49
valid_sources[0x26]	28597	1			T1	2		T3	57		T4	167
valid_sources[0x27]	29675	1			T1	3		T2	1		T3	76
valid_sources[0x28]	30717	1			T1	17		T3	68		T4	152
valid_sources[0x29]	32919	1			T1	8		T2	3		T3	42
valid_sources[0x2a]	30004	1			T1	21		T2	2		T3	26
valid_sources[0x2b]	29498	1			T1	18		T3	56		T4	158
valid_sources[0x2c]	34276	1			T1	7		T2	1		T3	56
valid_sources[0x2d]	27982	1			T1	11		T2	1		T3	70
valid_sources[0x2e]	35953	1			T1	36		T3	43		T4	168
valid_sources[0x2f]	29374	1			T1	27		T3	34		T4	135
valid_sources[0x30]	28070	1			T1	9		T2	2		T3	65
valid_sources[0x31]	33611	1			T1	19		T2	1		T3	34
valid_sources[0x32]	30383	1			T1	6		T2	1		T3	60
valid_sources[0x33]	27009	1			T1	5		T2	1		T3	61
valid_sources[0x34]	27614	1			T1	7		T3	80		T4	148
valid_sources[0x35]	30079	1			T1	8		T2	2		T3	60
valid_sources[0x36]	43433	1			T2	1		T3	37		T4	167
valid_sources[0x37]	68934	1			T1	13		T2	2		T3	42
valid_sources[0x38]	26664	1			T1	8		T3	36		T4	144
valid_sources[0x39]	30632	1			T1	3		T2	1		T3	40
valid_sources[0x3a]	31402	1			T1	7		T2	5		T3	47
valid_sources[0x3b]	29878	1			T1	9		T2	2		T3	29
valid_sources[0x3c]	30762	1			T2	2		T3	28		T4	148
valid_sources[0x3d]	34046	1			T1	24		T2	1		T3	64
valid_sources[0x3e]	34892	1			T1	6		T2	2		T3	54
valid_sources[0x3f]	31014	1			T1	9		T2	3		T3	39
valid_sources[0x40]	30943	1			T1	10		T2	2		T3	54
valid_sources[0x41]	30981	1			T1	14		T2	2		T3	30
valid_sources[0x42]	30399	1			T1	10		T2	2		T3	48
valid_sources[0x43]	25855	1			T1	18		T2	2		T3	39
valid_sources[0x44]	30632	1			T1	10		T2	3		T3	26
valid_sources[0x45]	26545	1			T1	10		T2	1		T3	41
valid_sources[0x46]	33349	1			T1	6		T2	1		T3	35
valid_sources[0x47]	32231	1			T1	11		T2	1		T3	40
valid_sources[0x48]	32840	1			T1	9		T2	1		T3	29
valid_sources[0x49]	31991	1			T1	24		T3	56		T4	158
valid_sources[0x4a]	29034	1			T1	3		T3	47		T4	132
valid_sources[0x4b]	31616	1			T1	11		T2	1		T3	41
valid_sources[0x4c]	31986	1			T1	11		T2	1		T3	55
valid_sources[0x4d]	33065	1			T2	2		T3	40		T4	159
valid_sources[0x4e]	42053	1			T1	14		T3	54		T4	146
valid_sources[0x4f]	35906	1			T1	4		T3	31		T4	142
valid_sources[0x50]	31677	1			T1	23		T2	1		T3	36
valid_sources[0x51]	30199	1			T1	7		T3	57		T4	127
valid_sources[0x52]	34572	1			T1	6		T3	60		T4	161
valid_sources[0x53]	30507	1			T1	37		T2	2		T3	55
valid_sources[0x54]	29542	1			T1	15		T2	1		T3	43
valid_sources[0x55]	29665	1			T1	11		T2	2		T3	49
valid_sources[0x56]	34289	1			T1	8		T2	1		T3	40
valid_sources[0x57]	28907	1			T1	7		T3	57		T4	131
valid_sources[0x58]	28145	1			T1	8		T2	2		T3	41
valid_sources[0x59]	29176	1			T1	4		T2	2		T3	32
valid_sources[0x5a]	30448	1			T1	1		T3	41		T4	153
valid_sources[0x5b]	29056	1			T1	19		T2	2		T3	51
valid_sources[0x5c]	27491	1			T1	3		T2	2		T3	54
valid_sources[0x5d]	28305	1			T1	9		T3	33		T4	146
valid_sources[0x5e]	27018	1			T1	3		T2	1		T3	61
valid_sources[0x5f]	32739	1			T1	10		T2	2		T3	76
valid_sources[0x60]	27783	1			T1	11		T2	2		T3	45
valid_sources[0x61]	29291	1			T1	9		T2	1		T3	71
valid_sources[0x62]	30182	1			T1	19		T2	2		T3	57
valid_sources[0x63]	66238	1			T1	13		T2	2		T3	21
valid_sources[0x64]	31971	1			T1	10		T2	1		T3	37
valid_sources[0x65]	30423	1			T1	17		T3	24		T4	180
valid_sources[0x66]	31022	1			T1	2		T3	66		T4	162
valid_sources[0x67]	32441	1			T1	5		T3	62		T4	135
valid_sources[0x68]	29571	1			T1	16		T2	1		T3	71
valid_sources[0x69]	32341	1			T3	49		T4	141		T5	12
valid_sources[0x6a]	29875	1			T1	8		T3	62		T4	143
valid_sources[0x6b]	35189	1			T1	21		T3	84		T4	158
valid_sources[0x6c]	30065	1			T1	16		T3	64		T4	127
valid_sources[0x6d]	30590	1			T1	5		T2	1		T3	51
valid_sources[0x6e]	39622	1			T1	17		T2	3		T3	43
valid_sources[0x6f]	31633	1			T1	14		T2	2		T3	77
valid_sources[0x70]	31683	1			T1	6		T2	2		T3	52
valid_sources[0x71]	27856	1			T1	14		T3	44		T4	142
valid_sources[0x72]	30332	1			T2	1		T3	45		T4	129
valid_sources[0x73]	37760	1			T1	2		T2	1		T3	36
valid_sources[0x74]	29131	1			T1	15		T2	1		T3	68
valid_sources[0x75]	29425	1			T1	1		T2	2		T3	60
valid_sources[0x76]	29456	1			T1	9		T3	84		T4	133
valid_sources[0x77]	31942	1			T1	16		T2	1		T3	41
valid_sources[0x78]	30629	1			T1	9		T2	2		T3	51
valid_sources[0x79]	36192	1			T1	9		T3	28		T4	170
valid_sources[0x7a]	30002	1			T2	1		T3	47		T4	156
valid_sources[0x7b]	28245	1			T1	11		T2	4		T3	59
valid_sources[0x7c]	30236	1			T1	5		T3	39		T4	127
valid_sources[0x7d]	30133	1			T1	3		T2	2		T3	41
valid_sources[0x7e]	30449	1			T1	13		T3	33		T4	149
valid_sources[0x7f]	34103	1			T1	2		T2	2		T3	50
valid_sources[0x80]	29671	1			T1	13		T3	23		T4	157

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1162757

1

T1

722

T2

19

T3

1460

values[0x0]

all_enables

biggest_size

1608569

1

T1

469

T2

18

T3

4781

values[0x1]

all_enables

biggest_size

1584255

1

T1

413

T2

22

T3

4857