Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3826520

1

T1

695

T2

231

T3

1288

full_word

4354833

1

T1

1604

T2

59

T3

11098

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8180913	1			T1	2299		T2	290		T3	12386
auto[TlIntgErrCmd]	146	1			T98	8		T103	2		T101	9
auto[TlIntgErrData]	168	1			T98	11		T103	5		T101	10
auto[TlIntgErrBoth]	126	1			T98	11		T103	3		T101	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4626652

1

T1

1408

T2

235

T3

2697

auto[1]

3554701

1

T1

891

T2

55

T3

9689

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3463461	1			T1	686		T2	216		T3	1237
auto[TlIntgErrNone]	partial	auto[1]	362652	1			T1	9		T2	15		T3	51
auto[TlIntgErrNone]	full_word	auto[0]	1163000	1			T1	722		T2	19		T3	1460
auto[TlIntgErrNone]	full_word	auto[1]	3191800	1			T1	882		T2	40		T3	9638
auto[TlIntgErrCmd]	partial	auto[0]	57	1			T103	2		T101	4		T128	1
auto[TlIntgErrCmd]	partial	auto[1]	80	1			T98	7		T101	5		T124	1
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T128	2		T121	1		T174	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T98	1		T126	1		T127	1
auto[TlIntgErrData]	partial	auto[0]	73	1			T98	4		T103	3		T101	3
auto[TlIntgErrData]	partial	auto[1]	80	1			T98	5		T103	2		T101	5
auto[TlIntgErrData]	full_word	auto[0]	5	1			T98	1		T126	1		T121	2
auto[TlIntgErrData]	full_word	auto[1]	10	1			T98	1		T101	2		T126	1
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T98	6		T101	3		T124	1
auto[TlIntgErrBoth]	partial	auto[1]	67	1			T98	4		T103	3		T101	7
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T98	1		T101	1		T124	1