Group : spi_device_env_pkg::busy_blocks_command_cg
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Group : spi_device_env_pkg::busy_blocks_command_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

5 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
spi_device_env_pkg.en4b_block_cmd_cg 100.00 1 100 1 64 64
spi_device_env_pkg.ex4b_block_cmd_cg 100.00 1 100 1 64 64
spi_device_env_pkg.upload_block_cmd_cg 100.00 1 100 1 64 64
spi_device_env_pkg.wrdi_block_cmd_cg 100.00 1 100 1 64 64
spi_device_env_pkg.wren_block_cmd_cg 100.00 1 100 1 64 64




Group Instance : spi_device_env_pkg.en4b_block_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device_env_pkg.en4b_block_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance spi_device_env_pkg.en4b_block_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_blocked_or_allowed 2 0 2 100.00 100 1 1 0



Group Instance : spi_device_env_pkg.ex4b_block_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device_env_pkg.ex4b_block_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance spi_device_env_pkg.ex4b_block_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_blocked_or_allowed 2 0 2 100.00 100 1 1 0



Group Instance : spi_device_env_pkg.upload_block_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device_env_pkg.upload_block_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance spi_device_env_pkg.upload_block_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_blocked_or_allowed 2 0 2 100.00 100 1 1 0



Group Instance : spi_device_env_pkg.wrdi_block_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device_env_pkg.wrdi_block_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance spi_device_env_pkg.wrdi_block_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_blocked_or_allowed 2 0 2 100.00 100 1 1 0



Group Instance : spi_device_env_pkg.wren_block_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device_env_pkg.wren_block_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance spi_device_env_pkg.wren_block_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_blocked_or_allowed 2 0 2 100.00 100 1 1 0


Summary for Variable cp_blocked_or_allowed

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_blocked_or_allowed

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
blocked 24 1 T50 1 T94 1 T179 3
allowed 1462 1 T3 7 T4 10 T8 4


Summary for Variable cp_blocked_or_allowed

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_blocked_or_allowed

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
blocked 32 1 T37 3 T50 1 T94 1
allowed 1474 1 T3 10 T4 5 T8 3


Summary for Variable cp_blocked_or_allowed

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_blocked_or_allowed

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
blocked 163 1 T4 3 T12 3 T37 4
allowed 4906 1 T3 24 T4 32 T8 30


Summary for Variable cp_blocked_or_allowed

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_blocked_or_allowed

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
blocked 21 1 T37 1 T48 1 T94 2
allowed 1444 1 T3 13 T4 5 T8 10


Summary for Variable cp_blocked_or_allowed

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_blocked_or_allowed

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
blocked 33 1 T37 2 T50 2 T94 1
allowed 1409 1 T3 14 T4 4 T7 4

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