Unified Coverage Report :: Module Instance :: tb.dut.u_readcmd.u_readsram.u_sram_fifo

Module Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.18	100.00	72.73			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.63	95.00	76.19			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.77	98.25	100.00		100.00	90.62	100.00	u_readsram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_readcmd.u_readsram.u_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.45	100.00	81.82			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.62	100.00	90.48			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.77	98.25	100.00		100.00	90.62	100.00	u_readsram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
62.10	85.71	31.25			71.43	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
59.07	84.62	36.11			55.56	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	56.48	84.00	40.00			45.45

Module Instance : tb.dut.u_spi_tpm.u_sram_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.32	100.00	77.27			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23	95.00	78.57			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.79	99.29	91.20		91.67	96.77	100.00	u_spi_tpm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.06	100.00	56.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	100.00	75.00			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	93.64	100.00	90.00			90.91

Module Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.14	94.52	60.33			73.08	84.62	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.67	80.00	31.25			71.43	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.32	82.50	47.22			55.56	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.14	94.52	60.33			73.08	84.62	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	63.15	84.00	60.00			45.45

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Total	Covered	Percent
Conditions	22	16	72.73
Logical	22	16	72.73
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	143322432	20107533	0	0
DepthKnown_A	143322432	113706946	0	0
RvalidKnown_A	143322432	113706946	0	0
WreadyKnown_A	143322432	113706946	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	143322432	20107533	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	20107533	0	0
T1	15248	14134	0	0
T2	1816	0	0	0
T3	393804	47967	0	0
T4	343353	17691	0	0
T5	15708	14464	0	0
T6	20678	3546	0	0
T7	27320	0	0	0
T8	773896	69153	0	0
T9	78680	23600	0	0
T10	25052	0	0	0
T12	0	37121	0	0
T23	0	7604	0	0
T26	0	31078	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	113706946	0	0
T1	15248	15248	0	0
T2	1816	0	0	0
T3	393804	391062	0	0
T4	343353	184520	0	0
T5	15708	15708	0	0
T6	20678	20678	0	0
T7	27320	27320	0	0
T8	773896	406930	0	0
T9	78680	78680	0	0
T10	25052	0	0	0
T11	0	10592	0	0
T12	0	479801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	113706946	0	0
T1	15248	15248	0	0
T2	1816	0	0	0
T3	393804	391062	0	0
T4	343353	184520	0	0
T5	15708	15708	0	0
T6	20678	20678	0	0
T7	27320	27320	0	0
T8	773896	406930	0	0
T9	78680	78680	0	0
T10	25052	0	0	0
T11	0	10592	0	0
T12	0	479801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	113706946	0	0
T1	15248	15248	0	0
T2	1816	0	0	0
T3	393804	391062	0	0
T4	343353	184520	0	0
T5	15708	15708	0	0
T6	20678	20678	0	0
T7	27320	27320	0	0
T8	773896	406930	0	0
T9	78680	78680	0	0
T10	25052	0	0	0
T11	0	10592	0	0
T12	0	479801	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	20107533	0	0
T1	15248	14134	0	0
T2	1816	0	0	0
T3	393804	47967	0	0
T4	343353	17691	0	0
T5	15708	14464	0	0
T6	20678	3546	0	0
T7	27320	0	0	0
T8	773896	69153	0	0
T9	78680	23600	0	0
T10	25052	0	0	0
T12	0	37121	0	0
T23	0	7604	0	0
T26	0	31078	0	0

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Total	Covered	Percent
Conditions	22	18	81.82
Logical	22	18	81.82
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	143322432	21120481	0	0
DepthKnown_A	143322432	113706946	0	0
RvalidKnown_A	143322432	113706946	0	0
WreadyKnown_A	143322432	113706946	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	143322432	21120481	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	21120481	0	0
T1	15248	14960	0	0
T2	1816	0	0	0
T3	393804	50050	0	0
T4	343353	18351	0	0
T5	15708	15412	0	0
T6	20678	3718	0	0
T7	27320	0	0	0
T8	773896	74562	0	0
T9	78680	24856	0	0
T10	25052	0	0	0
T12	0	38419	0	0
T23	0	8106	0	0
T26	0	32277	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	113706946	0	0
T1	15248	15248	0	0
T2	1816	0	0	0
T3	393804	391062	0	0
T4	343353	184520	0	0
T5	15708	15708	0	0
T6	20678	20678	0	0
T7	27320	27320	0	0
T8	773896	406930	0	0
T9	78680	78680	0	0
T10	25052	0	0	0
T11	0	10592	0	0
T12	0	479801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	113706946	0	0
T1	15248	15248	0	0
T2	1816	0	0	0
T3	393804	391062	0	0
T4	343353	184520	0	0
T5	15708	15708	0	0
T6	20678	20678	0	0
T7	27320	27320	0	0
T8	773896	406930	0	0
T9	78680	78680	0	0
T10	25052	0	0	0
T11	0	10592	0	0
T12	0	479801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	113706946	0	0
T1	15248	15248	0	0
T2	1816	0	0	0
T3	393804	391062	0	0
T4	343353	184520	0	0
T5	15708	15708	0	0
T6	20678	20678	0	0
T7	27320	27320	0	0
T8	773896	406930	0	0
T9	78680	78680	0	0
T10	25052	0	0	0
T11	0	10592	0	0
T12	0	479801	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	21120481	0	0
T1	15248	14960	0	0
T2	1816	0	0	0
T3	393804	50050	0	0
T4	343353	18351	0	0
T5	15708	15412	0	0
T6	20678	3718	0	0
T7	27320	0	0	0
T8	773896	74562	0	0
T9	78680	24856	0	0
T10	25052	0	0	0
T12	0	38419	0	0
T23	0	8106	0	0
T26	0	32277	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	12	85.71
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	1	50.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	0	1
			MISSING_ELSE
133	0	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	16	5	31.25
Logical	16	5	31.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (3'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		7	5	71.43
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	123	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	143322432	0	0	0
DepthKnown_A	143322432	113706946	0	0
RvalidKnown_A	143322432	113706946	0	0
WreadyKnown_A	143322432	113706946	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	143322432	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	113706946	0	0
T1	15248	15248	0	0
T2	1816	0	0	0
T3	393804	391062	0	0
T4	343353	184520	0	0
T5	15708	15708	0	0
T6	20678	20678	0	0
T7	27320	27320	0	0
T8	773896	406930	0	0
T9	78680	78680	0	0
T10	25052	0	0	0
T11	0	10592	0	0
T12	0	479801	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	113706946	0	0
T1	15248	15248	0	0
T2	1816	0	0	0
T3	393804	391062	0	0
T4	343353	184520	0	0
T5	15708	15708	0	0
T6	20678	20678	0	0
T7	27320	27320	0	0
T8	773896	406930	0	0
T9	78680	78680	0	0
T10	25052	0	0	0
T11	0	10592	0	0
T12	0	479801	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	113706946	0	0
T1	15248	15248	0	0
T2	1816	0	0	0
T3	393804	391062	0	0
T4	343353	184520	0	0
T5	15708	15708	0	0
T6	20678	20678	0	0
T7	27320	27320	0	0
T8	773896	406930	0	0
T9	78680	78680	0	0
T10	25052	0	0	0
T11	0	10592	0	0
T12	0	479801	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Total	Covered	Percent
Conditions	22	17	77.27
Logical	22	17	77.27
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T8

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T8
1	0	Not Covered
1	1	Covered	T2,T4,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T8
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T8
1	0	1	Covered	T2,T4,T8
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T8

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T8

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T8

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T8
1	0	Covered	T2,T4,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T8
0	0	Covered	T2,T4,T8

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	143322432	6208139	0	0
DepthKnown_A	143322432	28247285	0	0
RvalidKnown_A	143322432	28247285	0	0
WreadyKnown_A	143322432	28247285	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	143322432	6208139	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	6208139	0	0
T2	1816	920	0	0
T3	393804	0	0	0
T4	343353	52788	0	0
T5	15708	0	0	0
T6	20678	0	0	0
T7	27320	0	0	0
T8	773896	77247	0	0
T9	78680	0	0	0
T10	25052	0	0	0
T12	0	34086	0	0
T22	68118	0	0	0
T26	0	8923	0	0
T27	0	46884	0	0
T29	0	38	0	0
T30	0	724	0	0
T40	0	35531	0	0
T56	0	24074	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	28247285	0	0
T2	1816	1816	0	0
T3	393804	0	0	0
T4	343353	152504	0	0
T5	15708	0	0	0
T6	20678	0	0	0
T7	27320	0	0	0
T8	773896	358880	0	0
T9	78680	0	0	0
T10	25052	23664	0	0
T12	0	418400	0	0
T22	68118	65616	0	0
T26	0	21192	0	0
T27	0	131792	0	0
T28	0	720	0	0
T29	0	80	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	28247285	0	0
T2	1816	1816	0	0
T3	393804	0	0	0
T4	343353	152504	0	0
T5	15708	0	0	0
T6	20678	0	0	0
T7	27320	0	0	0
T8	773896	358880	0	0
T9	78680	0	0	0
T10	25052	23664	0	0
T12	0	418400	0	0
T22	68118	65616	0	0
T26	0	21192	0	0
T27	0	131792	0	0
T28	0	720	0	0
T29	0	80	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	28247285	0	0
T2	1816	1816	0	0
T3	393804	0	0	0
T4	343353	152504	0	0
T5	15708	0	0	0
T6	20678	0	0	0
T7	27320	0	0	0
T8	773896	358880	0	0
T9	78680	0	0	0
T10	25052	23664	0	0
T12	0	418400	0	0
T22	68118	65616	0	0
T26	0	21192	0	0
T27	0	131792	0	0
T28	0	720	0	0
T29	0	80	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	6208139	0	0
T2	1816	920	0	0
T3	393804	0	0	0
T4	343353	52788	0	0
T5	15708	0	0	0
T6	20678	0	0	0
T7	27320	0	0	0
T8	773896	77247	0	0
T9	78680	0	0	0
T10	25052	0	0	0
T12	0	34086	0	0
T22	68118	0	0	0
T26	0	8923	0	0
T27	0	46884	0	0
T29	0	38	0	0
T30	0	724	0	0
T40	0	35531	0	0
T56	0	24074	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	16	9	56.25
Logical	16	9	56.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T8

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T8
1	0	Not Covered
1	1	Covered	T2,T4,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T8
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T8

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (2'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T4,T8
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T8
0	0	Covered	T2,T4,T8

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	143322432	199448	0	0
DepthKnown_A	143322432	28247285	0	0
RvalidKnown_A	143322432	28247285	0	0
WreadyKnown_A	143322432	28247285	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	143322432	199448	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	199448	0	0
T2	1816	30	0	0
T3	393804	0	0	0
T4	343353	1692	0	0
T5	15708	0	0	0
T6	20678	0	0	0
T7	27320	0	0	0
T8	773896	2486	0	0
T9	78680	0	0	0
T10	25052	0	0	0
T12	0	1096	0	0
T22	68118	0	0	0
T26	0	286	0	0
T27	0	1511	0	0
T29	0	1	0	0
T30	0	22	0	0
T40	0	1140	0	0
T56	0	769	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	28247285	0	0
T2	1816	1816	0	0
T3	393804	0	0	0
T4	343353	152504	0	0
T5	15708	0	0	0
T6	20678	0	0	0
T7	27320	0	0	0
T8	773896	358880	0	0
T9	78680	0	0	0
T10	25052	23664	0	0
T12	0	418400	0	0
T22	68118	65616	0	0
T26	0	21192	0	0
T27	0	131792	0	0
T28	0	720	0	0
T29	0	80	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	28247285	0	0
T2	1816	1816	0	0
T3	393804	0	0	0
T4	343353	152504	0	0
T5	15708	0	0	0
T6	20678	0	0	0
T7	27320	0	0	0
T8	773896	358880	0	0
T9	78680	0	0	0
T10	25052	23664	0	0
T12	0	418400	0	0
T22	68118	65616	0	0
T26	0	21192	0	0
T27	0	131792	0	0
T28	0	720	0	0
T29	0	80	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	28247285	0	0
T2	1816	1816	0	0
T3	393804	0	0	0
T4	343353	152504	0	0
T5	15708	0	0	0
T6	20678	0	0	0
T7	27320	0	0	0
T8	773896	358880	0	0
T9	78680	0	0	0
T10	25052	23664	0	0
T12	0	418400	0	0
T22	68118	65616	0	0
T26	0	21192	0	0
T27	0	131792	0	0
T28	0	720	0	0
T29	0	80	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	199448	0	0
T2	1816	30	0	0
T3	393804	0	0	0
T4	343353	1692	0	0
T5	15708	0	0	0
T6	20678	0	0	0
T7	27320	0	0	0
T8	773896	2486	0	0
T9	78680	0	0	0
T10	25052	0	0	0
T12	0	1096	0	0
T22	68118	0	0	0
T26	0	286	0	0
T27	0	1511	0	0
T29	0	1	0	0
T30	0	22	0	0
T40	0	1140	0	0
T56	0	769	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	460171251	3078037	0	0
DepthKnown_A	460171251	460080176	0	0
RvalidKnown_A	460171251	460080176	0	0
WreadyKnown_A	460171251	460080176	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	460171251	3078037	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460171251	3078037	0	0
T1	34251	832	0	0
T2	5042	0	0	0
T3	163056	9152	0	0
T4	175988	4992	0	0
T5	8013	839	0	0
T6	52624	3729	0	0
T7	31130	832	0	0
T8	666727	11954	0	0
T9	81658	1856	0	0
T10	23571	0	0	0
T11	0	832	0	0
T12	0	9984	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460171251	460080176	0	0
T1	34251	34154	0	0
T2	5042	4946	0	0
T3	163056	163050	0	0
T4	175988	175978	0	0
T5	8013	7927	0	0
T6	52624	52574	0	0
T7	31130	31040	0	0
T8	666727	666390	0	0
T9	81658	81572	0	0
T10	23571	23472	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460171251	460080176	0	0
T1	34251	34154	0	0
T2	5042	4946	0	0
T3	163056	163050	0	0
T4	175988	175978	0	0
T5	8013	7927	0	0
T6	52624	52574	0	0
T7	31130	31040	0	0
T8	666727	666390	0	0
T9	81658	81572	0	0
T10	23571	23472	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460171251	460080176	0	0
T1	34251	34154	0	0
T2	5042	4946	0	0
T3	163056	163050	0	0
T4	175988	175978	0	0
T5	8013	7927	0	0
T6	52624	52574	0	0
T7	31130	31040	0	0
T8	666727	666390	0	0
T9	81658	81572	0	0
T10	23571	23472	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	460171251	3078037	0	0
T1	34251	832	0	0
T2	5042	0	0	0
T3	163056	9152	0	0
T4	175988	4992	0	0
T5	8013	839	0	0
T6	52624	3729	0	0
T7	31130	832	0	0
T8	666727	11954	0	0
T9	81658	1856	0	0
T10	23571	0	0	0
T11	0	832	0	0
T12	0	9984	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	12	80.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	1	50.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	0	1
111	1	1
112	0	1
			MISSING_ELSE
116	1	1
133	0	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	5	31.25
Logical	16	5	31.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	5	71.43
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	123	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	460171251	0	0	0
DepthKnown_A	460171251	460080176	0	0
RvalidKnown_A	460171251	460080176	0	0
WreadyKnown_A	460171251	460080176	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	460171251	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460171251	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460171251	460080176	0	0
T1	34251	34154	0	0
T2	5042	4946	0	0
T3	163056	163050	0	0
T4	175988	175978	0	0
T5	8013	7927	0	0
T6	52624	52574	0	0
T7	31130	31040	0	0
T8	666727	666390	0	0
T9	81658	81572	0	0
T10	23571	23472	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460171251	460080176	0	0
T1	34251	34154	0	0
T2	5042	4946	0	0
T3	163056	163050	0	0
T4	175988	175978	0	0
T5	8013	7927	0	0
T6	52624	52574	0	0
T7	31130	31040	0	0
T8	666727	666390	0	0
T9	81658	81572	0	0
T10	23571	23472	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460171251	460080176	0	0
T1	34251	34154	0	0
T2	5042	4946	0	0
T3	163056	163050	0	0
T4	175988	175978	0	0
T5	8013	7927	0	0
T6	52624	52574	0	0
T7	31130	31040	0	0
T8	666727	666390	0	0
T9	81658	81572	0	0
T10	23571	23472	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	460171251	0	0	0