Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	462298786	2783386	0	0
DepthKnown_A	462298786	462159433	0	0
RvalidKnown_A	462298786	462159433	0	0
WreadyKnown_A	462298786	462159433	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462298786	2783386	0	0
T1	34251	1663	0	0
T2	5042	0	0	0
T3	163056	14138	0	0
T4	175988	6654	0	0
T5	8013	1670	0	0
T6	52624	832	0	0
T7	31130	1663	0	0
T8	666727	9980	0	0
T9	81658	2876	0	0
T10	23571	0	0	0
T11	0	1663	0	0
T12	0	14970	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462298786	462159433	0	0
T1	34251	34154	0	0
T2	5042	4946	0	0
T3	163056	163050	0	0
T4	175988	175978	0	0
T5	8013	7927	0	0
T6	52624	52574	0	0
T7	31130	31040	0	0
T8	666727	666390	0	0
T9	81658	81572	0	0
T10	23571	23472	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462298786	462159433	0	0
T1	34251	34154	0	0
T2	5042	4946	0	0
T3	163056	163050	0	0
T4	175988	175978	0	0
T5	8013	7927	0	0
T6	52624	52574	0	0
T7	31130	31040	0	0
T8	666727	666390	0	0
T9	81658	81572	0	0
T10	23571	23472	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462298786	462159433	0	0
T1	34251	34154	0	0
T2	5042	4946	0	0
T3	163056	163050	0	0
T4	175988	175978	0	0
T5	8013	7927	0	0
T6	52624	52574	0	0
T7	31130	31040	0	0
T8	666727	666390	0	0
T9	81658	81572	0	0
T10	23571	23472	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	462298786	3113260	0	0
DepthKnown_A	462298786	462159433	0	0
RvalidKnown_A	462298786	462159433	0	0
WreadyKnown_A	462298786	462159433	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462298786	3113260	0	0
T1	34251	832	0	0
T2	5042	0	0	0
T3	163056	9152	0	0
T4	175988	4992	0	0
T5	8013	839	0	0
T6	52624	3729	0	0
T7	31130	832	0	0
T8	666727	11954	0	0
T9	81658	1856	0	0
T10	23571	0	0	0
T11	0	832	0	0
T12	0	9984	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462298786	462159433	0	0
T1	34251	34154	0	0
T2	5042	4946	0	0
T3	163056	163050	0	0
T4	175988	175978	0	0
T5	8013	7927	0	0
T6	52624	52574	0	0
T7	31130	31040	0	0
T8	666727	666390	0	0
T9	81658	81572	0	0
T10	23571	23472	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462298786	462159433	0	0
T1	34251	34154	0	0
T2	5042	4946	0	0
T3	163056	163050	0	0
T4	175988	175978	0	0
T5	8013	7927	0	0
T6	52624	52574	0	0
T7	31130	31040	0	0
T8	666727	666390	0	0
T9	81658	81572	0	0
T10	23571	23472	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462298786	462159433	0	0
T1	34251	34154	0	0
T2	5042	4946	0	0
T3	163056	163050	0	0
T4	175988	175978	0	0
T5	8013	7927	0	0
T6	52624	52574	0	0
T7	31130	31040	0	0
T8	666727	666390	0	0
T9	81658	81572	0	0
T10	23571	23472	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	462298786	193229	0	0
DepthKnown_A	462298786	462159433	0	0
RvalidKnown_A	462298786	462159433	0	0
WreadyKnown_A	462298786	462159433	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462298786	193229	0	0
T2	5042	12	0	0
T3	163056	339	0	0
T4	175988	1196	0	0
T5	8013	0	0	0
T6	52624	0	0	0
T7	31130	0	0	0
T8	666727	1510	0	0
T9	81658	0	0	0
T10	23571	0	0	0
T12	0	1756	0	0
T22	95928	0	0	0
T26	0	407	0	0
T27	0	706	0	0
T30	0	42	0	0
T39	0	257	0	0
T40	0	686	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462298786	462159433	0	0
T1	34251	34154	0	0
T2	5042	4946	0	0
T3	163056	163050	0	0
T4	175988	175978	0	0
T5	8013	7927	0	0
T6	52624	52574	0	0
T7	31130	31040	0	0
T8	666727	666390	0	0
T9	81658	81572	0	0
T10	23571	23472	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462298786	462159433	0	0
T1	34251	34154	0	0
T2	5042	4946	0	0
T3	163056	163050	0	0
T4	175988	175978	0	0
T5	8013	7927	0	0
T6	52624	52574	0	0
T7	31130	31040	0	0
T8	666727	666390	0	0
T9	81658	81572	0	0
T10	23571	23472	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462298786	462159433	0	0
T1	34251	34154	0	0
T2	5042	4946	0	0
T3	163056	163050	0	0
T4	175988	175978	0	0
T5	8013	7927	0	0
T6	52624	52574	0	0
T7	31130	31040	0	0
T8	666727	666390	0	0
T9	81658	81572	0	0
T10	23571	23472	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	462298786	426798	0	0
DepthKnown_A	462298786	462159433	0	0
RvalidKnown_A	462298786	462159433	0	0
WreadyKnown_A	462298786	462159433	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462298786	426798	0	0
T2	5042	12	0	0
T3	163056	339	0	0
T4	175988	1196	0	0
T5	8013	0	0	0
T6	52624	0	0	0
T7	31130	0	0	0
T8	666727	4490	0	0
T9	81658	0	0	0
T10	23571	0	0	0
T12	0	1751	0	0
T22	95928	0	0	0
T26	0	407	0	0
T27	0	706	0	0
T30	0	42	0	0
T39	0	257	0	0
T40	0	686	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462298786	462159433	0	0
T1	34251	34154	0	0
T2	5042	4946	0	0
T3	163056	163050	0	0
T4	175988	175978	0	0
T5	8013	7927	0	0
T6	52624	52574	0	0
T7	31130	31040	0	0
T8	666727	666390	0	0
T9	81658	81572	0	0
T10	23571	23472	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462298786	462159433	0	0
T1	34251	34154	0	0
T2	5042	4946	0	0
T3	163056	163050	0	0
T4	175988	175978	0	0
T5	8013	7927	0	0
T6	52624	52574	0	0
T7	31130	31040	0	0
T8	666727	666390	0	0
T9	81658	81572	0	0
T10	23571	23472	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462298786	462159433	0	0
T1	34251	34154	0	0
T2	5042	4946	0	0
T3	163056	163050	0	0
T4	175988	175978	0	0
T5	8013	7927	0	0
T6	52624	52574	0	0
T7	31130	31040	0	0
T8	666727	666390	0	0
T9	81658	81572	0	0
T10	23571	23472	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	462298786	6547393	0	0
DepthKnown_A	462298786	462159433	0	0
RvalidKnown_A	462298786	462159433	0	0
WreadyKnown_A	462298786	462159433	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462298786	6547393	0	0
T1	34251	1480	0	0
T2	5042	278	0	0
T3	163056	2895	0	0
T4	175988	31826	0	0
T5	8013	261	0	0
T6	52624	1237	0	0
T7	31130	1036	0	0
T8	666727	17022	0	0
T9	81658	3579	0	0
T10	23571	148	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462298786	462159433	0	0
T1	34251	34154	0	0
T2	5042	4946	0	0
T3	163056	163050	0	0
T4	175988	175978	0	0
T5	8013	7927	0	0
T6	52624	52574	0	0
T7	31130	31040	0	0
T8	666727	666390	0	0
T9	81658	81572	0	0
T10	23571	23472	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462298786	462159433	0	0
T1	34251	34154	0	0
T2	5042	4946	0	0
T3	163056	163050	0	0
T4	175988	175978	0	0
T5	8013	7927	0	0
T6	52624	52574	0	0
T7	31130	31040	0	0
T8	666727	666390	0	0
T9	81658	81572	0	0
T10	23571	23472	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462298786	462159433	0	0
T1	34251	34154	0	0
T2	5042	4946	0	0
T3	163056	163050	0	0
T4	175988	175978	0	0
T5	8013	7927	0	0
T6	52624	52574	0	0
T7	31130	31040	0	0
T8	666727	666390	0	0
T9	81658	81572	0	0
T10	23571	23472	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	462298786	12606987	0	0
DepthKnown_A	462298786	462159433	0	0
RvalidKnown_A	462298786	462159433	0	0
WreadyKnown_A	462298786	462159433	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462298786	12606987	0	0
T1	34251	6266	0	0
T2	5042	278	0	0
T3	163056	2895	0	0
T4	175988	31690	0	0
T5	8013	1114	0	0
T6	52624	5298	0	0
T7	31130	1036	0	0
T8	666727	45451	0	0
T9	81658	3576	0	0
T10	23571	148	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462298786	462159433	0	0
T1	34251	34154	0	0
T2	5042	4946	0	0
T3	163056	163050	0	0
T4	175988	175978	0	0
T5	8013	7927	0	0
T6	52624	52574	0	0
T7	31130	31040	0	0
T8	666727	666390	0	0
T9	81658	81572	0	0
T10	23571	23472	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462298786	462159433	0	0
T1	34251	34154	0	0
T2	5042	4946	0	0
T3	163056	163050	0	0
T4	175988	175978	0	0
T5	8013	7927	0	0
T6	52624	52574	0	0
T7	31130	31040	0	0
T8	666727	666390	0	0
T9	81658	81572	0	0
T10	23571	23472	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462298786	462159433	0	0
T1	34251	34154	0	0
T2	5042	4946	0	0
T3	163056	163050	0	0
T4	175988	175978	0	0
T5	8013	7927	0	0
T6	52624	52574	0	0
T7	31130	31040	0	0
T8	666727	666390	0	0
T9	81658	81572	0	0
T10	23571	23472	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0