Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T8
1	0	Covered	T2,T4,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T8
1	0	Unreachable
1	1	Covered	T2,T4,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T8
1	0	Covered	T3,T4,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T3,T4,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	746816115	602034407	0	0
CheckNGreaterZero_A	2928	2928	0	0
GntImpliesReady_A	746816115	3604653	0	0
GntImpliesValid_A	746816115	3604653	0	0
GrantKnown_A	746816115	602034407	0	0
IdxKnown_A	746816115	602034407	0	0
IndexIsCorrect_A	746816115	3604653	0	0
LockArbDecision_A	746816115	0	0	0
NoReadyValidNoGrant_A	746816115	0	0	0
ReadyAndValidImplyGrant_A	746816115	3604653	0	0
ReqAndReadyImplyGrant_A	746816115	3604653	0	0
ReqImpliesValid_A	746816115	3604653	0	0
ReqStaysHighUntilGranted0_M	746816115	0	0	0
RoundRobin_A	746816115	5	0	976
ValidKnown_A	746816115	602034407	0	0
gen_data_port_assertion.DataFlow_A	746816115	3604653	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746816115	602034407	0	0
T1	49499	49402	0	0
T2	8674	6762	0	0
T3	950664	554112	0	0
T4	862694	513002	0	0
T5	39429	23635	0	0
T6	93980	73252	0	0
T7	85770	58360	0	0
T8	2214519	1432200	0	0
T9	239018	160252	0	0
T10	73675	47136	0	0
T11	0	10592	0	0
T12	0	898201	0	0
T22	68118	65616	0	0
T26	0	21192	0	0
T27	0	131792	0	0
T28	0	720	0	0
T29	0	80	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2928	2928	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746816115	3604653	0	0
T1	34251	832	0	0
T2	6858	112	0	0
T3	950664	10899	0	0
T4	862694	14361	0	0
T5	39429	832	0	0
T6	93980	832	0	0
T7	85770	832	0	0
T8	2214519	21903	0	0
T9	239018	1856	0	0
T10	73675	0	0	0
T11	10592	832	0	0
T12	0	12396	0	0
T22	136236	0	0	0
T26	0	2108	0	0
T27	0	4364	0	0
T29	0	2	0	0
T30	0	187	0	0
T37	0	4952	0	0
T39	0	1702	0	0
T40	0	3923	0	0
T53	0	4	0	0
T56	0	2358	0	0
T57	0	2	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746816115	3604653	0	0
T1	34251	832	0	0
T2	6858	112	0	0
T3	950664	10899	0	0
T4	862694	14361	0	0
T5	39429	832	0	0
T6	93980	832	0	0
T7	85770	832	0	0
T8	2214519	21903	0	0
T9	239018	1856	0	0
T10	73675	0	0	0
T11	10592	832	0	0
T12	0	12396	0	0
T22	136236	0	0	0
T26	0	2108	0	0
T27	0	4364	0	0
T29	0	2	0	0
T30	0	187	0	0
T37	0	4952	0	0
T39	0	1702	0	0
T40	0	3923	0	0
T53	0	4	0	0
T56	0	2358	0	0
T57	0	2	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746816115	602034407	0	0
T1	49499	49402	0	0
T2	8674	6762	0	0
T3	950664	554112	0	0
T4	862694	513002	0	0
T5	39429	23635	0	0
T6	93980	73252	0	0
T7	85770	58360	0	0
T8	2214519	1432200	0	0
T9	239018	160252	0	0
T10	73675	47136	0	0
T11	0	10592	0	0
T12	0	898201	0	0
T22	68118	65616	0	0
T26	0	21192	0	0
T27	0	131792	0	0
T28	0	720	0	0
T29	0	80	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746816115	602034407	0	0
T1	49499	49402	0	0
T2	8674	6762	0	0
T3	950664	554112	0	0
T4	862694	513002	0	0
T5	39429	23635	0	0
T6	93980	73252	0	0
T7	85770	58360	0	0
T8	2214519	1432200	0	0
T9	239018	160252	0	0
T10	73675	47136	0	0
T11	0	10592	0	0
T12	0	898201	0	0
T22	68118	65616	0	0
T26	0	21192	0	0
T27	0	131792	0	0
T28	0	720	0	0
T29	0	80	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746816115	3604653	0	0
T1	34251	832	0	0
T2	6858	112	0	0
T3	950664	10899	0	0
T4	862694	14361	0	0
T5	39429	832	0	0
T6	93980	832	0	0
T7	85770	832	0	0
T8	2214519	21903	0	0
T9	239018	1856	0	0
T10	73675	0	0	0
T11	10592	832	0	0
T12	0	12396	0	0
T22	136236	0	0	0
T26	0	2108	0	0
T27	0	4364	0	0
T29	0	2	0	0
T30	0	187	0	0
T37	0	4952	0	0
T39	0	1702	0	0
T40	0	3923	0	0
T53	0	4	0	0
T56	0	2358	0	0
T57	0	2	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746816115	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746816115	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746816115	3604653	0	0
T1	34251	832	0	0
T2	6858	112	0	0
T3	950664	10899	0	0
T4	862694	14361	0	0
T5	39429	832	0	0
T6	93980	832	0	0
T7	85770	832	0	0
T8	2214519	21903	0	0
T9	239018	1856	0	0
T10	73675	0	0	0
T11	10592	832	0	0
T12	0	12396	0	0
T22	136236	0	0	0
T26	0	2108	0	0
T27	0	4364	0	0
T29	0	2	0	0
T30	0	187	0	0
T37	0	4952	0	0
T39	0	1702	0	0
T40	0	3923	0	0
T53	0	4	0	0
T56	0	2358	0	0
T57	0	2	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746816115	3604653	0	0
T1	34251	832	0	0
T2	6858	112	0	0
T3	950664	10899	0	0
T4	862694	14361	0	0
T5	39429	832	0	0
T6	93980	832	0	0
T7	85770	832	0	0
T8	2214519	21903	0	0
T9	239018	1856	0	0
T10	73675	0	0	0
T11	10592	832	0	0
T12	0	12396	0	0
T22	136236	0	0	0
T26	0	2108	0	0
T27	0	4364	0	0
T29	0	2	0	0
T30	0	187	0	0
T37	0	4952	0	0
T39	0	1702	0	0
T40	0	3923	0	0
T53	0	4	0	0
T56	0	2358	0	0
T57	0	2	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746816115	3604653	0	0
T1	34251	832	0	0
T2	6858	112	0	0
T3	950664	10899	0	0
T4	862694	14361	0	0
T5	39429	832	0	0
T6	93980	832	0	0
T7	85770	832	0	0
T8	2214519	21903	0	0
T9	239018	1856	0	0
T10	73675	0	0	0
T11	10592	832	0	0
T12	0	12396	0	0
T22	136236	0	0	0
T26	0	2108	0	0
T27	0	4364	0	0
T29	0	2	0	0
T30	0	187	0	0
T37	0	4952	0	0
T39	0	1702	0	0
T40	0	3923	0	0
T53	0	4	0	0
T56	0	2358	0	0
T57	0	2	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	746816115	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746816115	5	0	976
T38	277497	1	0	1
T46	489012	1	0	1
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	280198	0	0	1
T62	18625	0	0	1
T63	31717	0	0	1
T64	76813	0	0	1
T65	502129	0	0	1
T66	30268	0	0	1
T67	7111	0	0	1
T68	4397	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746816115	602034407	0	0
T1	49499	49402	0	0
T2	8674	6762	0	0
T3	950664	554112	0	0
T4	862694	513002	0	0
T5	39429	23635	0	0
T6	93980	73252	0	0
T7	85770	58360	0	0
T8	2214519	1432200	0	0
T9	239018	160252	0	0
T10	73675	47136	0	0
T11	0	10592	0	0
T12	0	898201	0	0
T22	68118	65616	0	0
T26	0	21192	0	0
T27	0	131792	0	0
T28	0	720	0	0
T29	0	80	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746816115	3604653	0	0
T1	34251	832	0	0
T2	6858	112	0	0
T3	950664	10899	0	0
T4	862694	14361	0	0
T5	39429	832	0	0
T6	93980	832	0	0
T7	85770	832	0	0
T8	2214519	21903	0	0
T9	239018	1856	0	0
T10	73675	0	0	0
T11	10592	832	0	0
T12	0	12396	0	0
T22	136236	0	0	0
T26	0	2108	0	0
T27	0	4364	0	0
T29	0	2	0	0
T30	0	187	0	0
T37	0	4952	0	0
T39	0	1702	0	0
T40	0	3923	0	0
T53	0	4	0	0
T56	0	2358	0	0
T57	0	2	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T8
1	0	Covered	T2,T4,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T8
1	0	Unreachable
1	1	Covered	T2,T4,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T8
0	0	1	Unreachable
0	0	0	Covered	T2,T4,T8

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	143322432	28247285	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	143322432	648664	0	0
GntImpliesValid_A	143322432	648664	0	0
GrantKnown_A	143322432	28247285	0	0
IdxKnown_A	143322432	28247285	0	0
IndexIsCorrect_A	143322432	648664	0	0
LockArbDecision_A	143322432	0	0	0
NoReadyValidNoGrant_A	143322432	0	0	0
ReadyAndValidImplyGrant_A	143322432	648664	0	0
ReqAndReadyImplyGrant_A	143322432	648664	0	0
ReqImpliesValid_A	143322432	648664	0	0
ReqStaysHighUntilGranted0_M	143322432	0	0	0
RoundRobin_A	143322432	0	0	0
ValidKnown_A	143322432	28247285	0	0
gen_data_port_assertion.DataFlow_A	143322432	648664	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	28247285	0	0
T2	1816	1816	0	0
T3	393804	0	0	0
T4	343353	152504	0	0
T5	15708	0	0	0
T6	20678	0	0	0
T7	27320	0	0	0
T8	773896	358880	0	0
T9	78680	0	0	0
T10	25052	23664	0	0
T12	0	418400	0	0
T22	68118	65616	0	0
T26	0	21192	0	0
T27	0	131792	0	0
T28	0	720	0	0
T29	0	80	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	648664	0	0
T2	1816	70	0	0
T3	393804	0	0	0
T4	343353	6208	0	0
T5	15708	0	0	0
T6	20678	0	0	0
T7	27320	0	0	0
T8	773896	7007	0	0
T9	78680	0	0	0
T10	25052	0	0	0
T12	0	4735	0	0
T22	68118	0	0	0
T26	0	958	0	0
T27	0	4364	0	0
T29	0	2	0	0
T30	0	187	0	0
T40	0	3912	0	0
T56	0	2358	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	648664	0	0
T2	1816	70	0	0
T3	393804	0	0	0
T4	343353	6208	0	0
T5	15708	0	0	0
T6	20678	0	0	0
T7	27320	0	0	0
T8	773896	7007	0	0
T9	78680	0	0	0
T10	25052	0	0	0
T12	0	4735	0	0
T22	68118	0	0	0
T26	0	958	0	0
T27	0	4364	0	0
T29	0	2	0	0
T30	0	187	0	0
T40	0	3912	0	0
T56	0	2358	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	28247285	0	0
T2	1816	1816	0	0
T3	393804	0	0	0
T4	343353	152504	0	0
T5	15708	0	0	0
T6	20678	0	0	0
T7	27320	0	0	0
T8	773896	358880	0	0
T9	78680	0	0	0
T10	25052	23664	0	0
T12	0	418400	0	0
T22	68118	65616	0	0
T26	0	21192	0	0
T27	0	131792	0	0
T28	0	720	0	0
T29	0	80	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	28247285	0	0
T2	1816	1816	0	0
T3	393804	0	0	0
T4	343353	152504	0	0
T5	15708	0	0	0
T6	20678	0	0	0
T7	27320	0	0	0
T8	773896	358880	0	0
T9	78680	0	0	0
T10	25052	23664	0	0
T12	0	418400	0	0
T22	68118	65616	0	0
T26	0	21192	0	0
T27	0	131792	0	0
T28	0	720	0	0
T29	0	80	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	648664	0	0
T2	1816	70	0	0
T3	393804	0	0	0
T4	343353	6208	0	0
T5	15708	0	0	0
T6	20678	0	0	0
T7	27320	0	0	0
T8	773896	7007	0	0
T9	78680	0	0	0
T10	25052	0	0	0
T12	0	4735	0	0
T22	68118	0	0	0
T26	0	958	0	0
T27	0	4364	0	0
T29	0	2	0	0
T30	0	187	0	0
T40	0	3912	0	0
T56	0	2358	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	648664	0	0
T2	1816	70	0	0
T3	393804	0	0	0
T4	343353	6208	0	0
T5	15708	0	0	0
T6	20678	0	0	0
T7	27320	0	0	0
T8	773896	7007	0	0
T9	78680	0	0	0
T10	25052	0	0	0
T12	0	4735	0	0
T22	68118	0	0	0
T26	0	958	0	0
T27	0	4364	0	0
T29	0	2	0	0
T30	0	187	0	0
T40	0	3912	0	0
T56	0	2358	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	648664	0	0
T2	1816	70	0	0
T3	393804	0	0	0
T4	343353	6208	0	0
T5	15708	0	0	0
T6	20678	0	0	0
T7	27320	0	0	0
T8	773896	7007	0	0
T9	78680	0	0	0
T10	25052	0	0	0
T12	0	4735	0	0
T22	68118	0	0	0
T26	0	958	0	0
T27	0	4364	0	0
T29	0	2	0	0
T30	0	187	0	0
T40	0	3912	0	0
T56	0	2358	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	648664	0	0
T2	1816	70	0	0
T3	393804	0	0	0
T4	343353	6208	0	0
T5	15708	0	0	0
T6	20678	0	0	0
T7	27320	0	0	0
T8	773896	7007	0	0
T9	78680	0	0	0
T10	25052	0	0	0
T12	0	4735	0	0
T22	68118	0	0	0
T26	0	958	0	0
T27	0	4364	0	0
T29	0	2	0	0
T30	0	187	0	0
T40	0	3912	0	0
T56	0	2358	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	28247285	0	0
T2	1816	1816	0	0
T3	393804	0	0	0
T4	343353	152504	0	0
T5	15708	0	0	0
T6	20678	0	0	0
T7	27320	0	0	0
T8	773896	358880	0	0
T9	78680	0	0	0
T10	25052	23664	0	0
T12	0	418400	0	0
T22	68118	65616	0	0
T26	0	21192	0	0
T27	0	131792	0	0
T28	0	720	0	0
T29	0	80	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	648664	0	0
T2	1816	70	0	0
T3	393804	0	0	0
T4	343353	6208	0	0
T5	15708	0	0	0
T6	20678	0	0	0
T7	27320	0	0	0
T8	773896	7007	0	0
T9	78680	0	0	0
T10	25052	0	0	0
T12	0	4735	0	0
T22	68118	0	0	0
T26	0	958	0	0
T27	0	4364	0	0
T29	0	2	0	0
T30	0	187	0	0
T40	0	3912	0	0
T56	0	2358	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T8
1	0	Covered	T3,T4,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T3,T4,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T8
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	143322432	113706946	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	143322432	728518	0	0
GntImpliesValid_A	143322432	728518	0	0
GrantKnown_A	143322432	113706946	0	0
IdxKnown_A	143322432	113706946	0	0
IndexIsCorrect_A	143322432	728518	0	0
LockArbDecision_A	143322432	0	0	0
NoReadyValidNoGrant_A	143322432	0	0	0
ReadyAndValidImplyGrant_A	143322432	728518	0	0
ReqAndReadyImplyGrant_A	143322432	728518	0	0
ReqImpliesValid_A	143322432	728518	0	0
ReqStaysHighUntilGranted0_M	143322432	0	0	0
RoundRobin_A	143322432	0	0	0
ValidKnown_A	143322432	113706946	0	0
gen_data_port_assertion.DataFlow_A	143322432	728518	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	113706946	0	0
T1	15248	15248	0	0
T2	1816	0	0	0
T3	393804	391062	0	0
T4	343353	184520	0	0
T5	15708	15708	0	0
T6	20678	20678	0	0
T7	27320	27320	0	0
T8	773896	406930	0	0
T9	78680	78680	0	0
T10	25052	0	0	0
T11	0	10592	0	0
T12	0	479801	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	728518	0	0
T3	393804	1386	0	0
T4	343353	265	0	0
T5	15708	0	0	0
T6	20678	0	0	0
T7	27320	0	0	0
T8	773896	4233	0	0
T9	78680	0	0	0
T10	25052	0	0	0
T11	10592	0	0	0
T12	0	7661	0	0
T22	68118	0	0	0
T26	0	1150	0	0
T37	0	4952	0	0
T39	0	1702	0	0
T40	0	11	0	0
T53	0	4	0	0
T57	0	2	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	728518	0	0
T3	393804	1386	0	0
T4	343353	265	0	0
T5	15708	0	0	0
T6	20678	0	0	0
T7	27320	0	0	0
T8	773896	4233	0	0
T9	78680	0	0	0
T10	25052	0	0	0
T11	10592	0	0	0
T12	0	7661	0	0
T22	68118	0	0	0
T26	0	1150	0	0
T37	0	4952	0	0
T39	0	1702	0	0
T40	0	11	0	0
T53	0	4	0	0
T57	0	2	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	113706946	0	0
T1	15248	15248	0	0
T2	1816	0	0	0
T3	393804	391062	0	0
T4	343353	184520	0	0
T5	15708	15708	0	0
T6	20678	20678	0	0
T7	27320	27320	0	0
T8	773896	406930	0	0
T9	78680	78680	0	0
T10	25052	0	0	0
T11	0	10592	0	0
T12	0	479801	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	113706946	0	0
T1	15248	15248	0	0
T2	1816	0	0	0
T3	393804	391062	0	0
T4	343353	184520	0	0
T5	15708	15708	0	0
T6	20678	20678	0	0
T7	27320	27320	0	0
T8	773896	406930	0	0
T9	78680	78680	0	0
T10	25052	0	0	0
T11	0	10592	0	0
T12	0	479801	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	728518	0	0
T3	393804	1386	0	0
T4	343353	265	0	0
T5	15708	0	0	0
T6	20678	0	0	0
T7	27320	0	0	0
T8	773896	4233	0	0
T9	78680	0	0	0
T10	25052	0	0	0
T11	10592	0	0	0
T12	0	7661	0	0
T22	68118	0	0	0
T26	0	1150	0	0
T37	0	4952	0	0
T39	0	1702	0	0
T40	0	11	0	0
T53	0	4	0	0
T57	0	2	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	728518	0	0
T3	393804	1386	0	0
T4	343353	265	0	0
T5	15708	0	0	0
T6	20678	0	0	0
T7	27320	0	0	0
T8	773896	4233	0	0
T9	78680	0	0	0
T10	25052	0	0	0
T11	10592	0	0	0
T12	0	7661	0	0
T22	68118	0	0	0
T26	0	1150	0	0
T37	0	4952	0	0
T39	0	1702	0	0
T40	0	11	0	0
T53	0	4	0	0
T57	0	2	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	728518	0	0
T3	393804	1386	0	0
T4	343353	265	0	0
T5	15708	0	0	0
T6	20678	0	0	0
T7	27320	0	0	0
T8	773896	4233	0	0
T9	78680	0	0	0
T10	25052	0	0	0
T11	10592	0	0	0
T12	0	7661	0	0
T22	68118	0	0	0
T26	0	1150	0	0
T37	0	4952	0	0
T39	0	1702	0	0
T40	0	11	0	0
T53	0	4	0	0
T57	0	2	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	728518	0	0
T3	393804	1386	0	0
T4	343353	265	0	0
T5	15708	0	0	0
T6	20678	0	0	0
T7	27320	0	0	0
T8	773896	4233	0	0
T9	78680	0	0	0
T10	25052	0	0	0
T11	10592	0	0	0
T12	0	7661	0	0
T22	68118	0	0	0
T26	0	1150	0	0
T37	0	4952	0	0
T39	0	1702	0	0
T40	0	11	0	0
T53	0	4	0	0
T57	0	2	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	113706946	0	0
T1	15248	15248	0	0
T2	1816	0	0	0
T3	393804	391062	0	0
T4	343353	184520	0	0
T5	15708	15708	0	0
T6	20678	20678	0	0
T7	27320	27320	0	0
T8	773896	406930	0	0
T9	78680	78680	0	0
T10	25052	0	0	0
T11	0	10592	0	0
T12	0	479801	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143322432	728518	0	0
T3	393804	1386	0	0
T4	343353	265	0	0
T5	15708	0	0	0
T6	20678	0	0	0
T7	27320	0	0	0
T8	773896	4233	0	0
T9	78680	0	0	0
T10	25052	0	0	0
T11	10592	0	0	0
T12	0	7661	0	0
T22	68118	0	0	0
T26	0	1150	0	0
T37	0	4952	0	0
T39	0	1702	0	0
T40	0	11	0	0
T53	0	4	0	0
T57	0	2	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	460171251	460080176	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	460171251	2227471	0	0
GntImpliesValid_A	460171251	2227471	0	0
GrantKnown_A	460171251	460080176	0	0
IdxKnown_A	460171251	460080176	0	0
IndexIsCorrect_A	460171251	2227471	0	0
LockArbDecision_A	460171251	0	0	0
NoReadyValidNoGrant_A	460171251	0	0	0
ReadyAndValidImplyGrant_A	460171251	2227471	0	0
ReqAndReadyImplyGrant_A	460171251	2227471	0	0
ReqImpliesValid_A	460171251	2227471	0	0
ReqStaysHighUntilGranted0_M	460171251	0	0	0
RoundRobin_A	460171251	5	0	976
ValidKnown_A	460171251	460080176	0	0
gen_data_port_assertion.DataFlow_A	460171251	2227471	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460171251	460080176	0	0
T1	34251	34154	0	0
T2	5042	4946	0	0
T3	163056	163050	0	0
T4	175988	175978	0	0
T5	8013	7927	0	0
T6	52624	52574	0	0
T7	31130	31040	0	0
T8	666727	666390	0	0
T9	81658	81572	0	0
T10	23571	23472	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460171251	2227471	0	0
T1	34251	832	0	0
T2	5042	42	0	0
T3	163056	9513	0	0
T4	175988	7888	0	0
T5	8013	832	0	0
T6	52624	832	0	0
T7	31130	832	0	0
T8	666727	10663	0	0
T9	81658	1856	0	0
T10	23571	0	0	0
T11	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460171251	2227471	0	0
T1	34251	832	0	0
T2	5042	42	0	0
T3	163056	9513	0	0
T4	175988	7888	0	0
T5	8013	832	0	0
T6	52624	832	0	0
T7	31130	832	0	0
T8	666727	10663	0	0
T9	81658	1856	0	0
T10	23571	0	0	0
T11	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460171251	460080176	0	0
T1	34251	34154	0	0
T2	5042	4946	0	0
T3	163056	163050	0	0
T4	175988	175978	0	0
T5	8013	7927	0	0
T6	52624	52574	0	0
T7	31130	31040	0	0
T8	666727	666390	0	0
T9	81658	81572	0	0
T10	23571	23472	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460171251	460080176	0	0
T1	34251	34154	0	0
T2	5042	4946	0	0
T3	163056	163050	0	0
T4	175988	175978	0	0
T5	8013	7927	0	0
T6	52624	52574	0	0
T7	31130	31040	0	0
T8	666727	666390	0	0
T9	81658	81572	0	0
T10	23571	23472	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460171251	2227471	0	0
T1	34251	832	0	0
T2	5042	42	0	0
T3	163056	9513	0	0
T4	175988	7888	0	0
T5	8013	832	0	0
T6	52624	832	0	0
T7	31130	832	0	0
T8	666727	10663	0	0
T9	81658	1856	0	0
T10	23571	0	0	0
T11	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460171251	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460171251	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460171251	2227471	0	0
T1	34251	832	0	0
T2	5042	42	0	0
T3	163056	9513	0	0
T4	175988	7888	0	0
T5	8013	832	0	0
T6	52624	832	0	0
T7	31130	832	0	0
T8	666727	10663	0	0
T9	81658	1856	0	0
T10	23571	0	0	0
T11	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460171251	2227471	0	0
T1	34251	832	0	0
T2	5042	42	0	0
T3	163056	9513	0	0
T4	175988	7888	0	0
T5	8013	832	0	0
T6	52624	832	0	0
T7	31130	832	0	0
T8	666727	10663	0	0
T9	81658	1856	0	0
T10	23571	0	0	0
T11	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460171251	2227471	0	0
T1	34251	832	0	0
T2	5042	42	0	0
T3	163056	9513	0	0
T4	175988	7888	0	0
T5	8013	832	0	0
T6	52624	832	0	0
T7	31130	832	0	0
T8	666727	10663	0	0
T9	81658	1856	0	0
T10	23571	0	0	0
T11	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	460171251	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460171251	5	0	976
T38	277497	1	0	1
T46	489012	1	0	1
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	280198	0	0	1
T62	18625	0	0	1
T63	31717	0	0	1
T64	76813	0	0	1
T65	502129	0	0	1
T66	30268	0	0	1
T67	7111	0	0	1
T68	4397	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460171251	460080176	0	0
T1	34251	34154	0	0
T2	5042	4946	0	0
T3	163056	163050	0	0
T4	175988	175978	0	0
T5	8013	7927	0	0
T6	52624	52574	0	0
T7	31130	31040	0	0
T8	666727	666390	0	0
T9	81658	81572	0	0
T10	23571	23472	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460171251	2227471	0	0
T1	34251	832	0	0
T2	5042	42	0	0
T3	163056	9513	0	0
T4	175988	7888	0	0
T5	8013	832	0	0
T6	52624	832	0	0
T7	31130	832	0	0
T8	666727	10663	0	0
T9	81658	1856	0	0
T10	23571	0	0	0
T11	0	832	0	0