Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3208560	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4115163

1

T1

410

T2

9

T3

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3991901	1			T1	1		T2	1		T3	1
values[0x0]	1665137	1			T1	256		T2	7		T3	11
values[0x1]	1666685	1			T1	241		T2	6		T3	17

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2292363	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5031360

1

T1

427

T2

10

T3

25

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28185	1			T4	8		T5	2		T8	9
valid_sources[0x01]	33661	1			T1	8		T4	21		T5	7
valid_sources[0x02]	28117	1			T4	22		T8	7		T11	4
valid_sources[0x03]	27491	1			T4	8		T5	1		T8	4
valid_sources[0x04]	29373	1			T4	12		T8	8		T10	5
valid_sources[0x05]	27540	1			T4	11		T5	15		T8	8
valid_sources[0x06]	30117	1			T4	10		T5	1		T8	3
valid_sources[0x07]	32142	1			T3	1		T4	21		T8	8
valid_sources[0x08]	28932	1			T4	20		T5	2		T8	6
valid_sources[0x09]	28213	1			T1	3		T4	23		T5	6
valid_sources[0x0a]	26313	1			T4	11		T5	1		T8	2
valid_sources[0x0b]	28518	1			T4	4		T5	4		T8	7
valid_sources[0x0c]	26818	1			T1	13		T4	5		T8	6
valid_sources[0x0d]	32452	1			T4	4		T5	20		T8	12
valid_sources[0x0e]	29987	1			T1	11		T4	15		T5	8
valid_sources[0x0f]	27816	1			T4	20		T5	2		T8	5
valid_sources[0x10]	26626	1			T4	22		T5	2		T8	8
valid_sources[0x11]	26664	1			T4	26		T5	8		T8	2
valid_sources[0x12]	29758	1			T4	10		T5	11		T8	7
valid_sources[0x13]	28798	1			T4	12		T5	1		T8	10
valid_sources[0x14]	26934	1			T4	21		T5	5		T8	10
valid_sources[0x15]	26959	1			T4	34		T5	10		T8	6
valid_sources[0x16]	25918	1			T4	11		T5	3		T8	4
valid_sources[0x17]	27071	1			T4	7		T8	5		T10	1
valid_sources[0x18]	27772	1			T4	9		T8	2		T10	14
valid_sources[0x19]	28961	1			T4	4		T5	1		T8	14
valid_sources[0x1a]	26430	1			T4	12		T5	5		T8	4
valid_sources[0x1b]	26932	1			T4	7		T5	10		T8	5
valid_sources[0x1c]	27139	1			T4	11		T5	4		T8	5
valid_sources[0x1d]	28912	1			T1	2		T4	17		T5	1
valid_sources[0x1e]	30135	1			T4	9		T5	3		T8	4
valid_sources[0x1f]	26547	1			T4	5		T5	1		T8	3
valid_sources[0x20]	28810	1			T4	4		T5	4		T8	9
valid_sources[0x21]	26996	1			T2	1		T4	7		T8	13
valid_sources[0x22]	27492	1			T4	9		T5	1		T8	10
valid_sources[0x23]	34374	1			T4	4		T8	4		T11	5
valid_sources[0x24]	27105	1			T4	22		T5	2		T8	6
valid_sources[0x25]	25976	1			T1	6		T3	1		T4	11
valid_sources[0x26]	27464	1			T1	8		T4	23		T5	4
valid_sources[0x27]	30160	1			T2	2		T4	11		T5	5
valid_sources[0x28]	33836	1			T4	4		T5	4		T8	1
valid_sources[0x29]	25147	1			T1	4		T4	15		T5	16
valid_sources[0x2a]	29446	1			T3	1		T4	9		T8	8
valid_sources[0x2b]	26706	1			T4	12		T5	10		T8	6
valid_sources[0x2c]	28235	1			T4	19		T8	12		T10	7
valid_sources[0x2d]	39623	1			T4	13		T5	5		T8	6
valid_sources[0x2e]	27197	1			T4	10		T6	11		T8	8
valid_sources[0x2f]	28305	1			T4	15		T8	15		T10	7
valid_sources[0x30]	28350	1			T4	22		T8	6		T11	11
valid_sources[0x31]	28705	1			T4	3		T5	10		T8	7
valid_sources[0x32]	29562	1			T4	13		T8	11		T11	2
valid_sources[0x33]	27985	1			T1	1		T4	12		T8	8
valid_sources[0x34]	32800	1			T4	9		T5	2		T8	5
valid_sources[0x35]	27159	1			T3	1		T4	11		T5	3
valid_sources[0x36]	26304	1			T4	8		T5	2		T8	6
valid_sources[0x37]	30220	1			T4	16		T5	24		T8	5
valid_sources[0x38]	29361	1			T4	14		T5	9		T8	4
valid_sources[0x39]	27287	1			T4	21		T5	5		T8	8
valid_sources[0x3a]	26201	1			T4	3		T8	9		T10	8
valid_sources[0x3b]	31829	1			T2	4		T4	13		T8	4
valid_sources[0x3c]	26052	1			T4	20		T5	12		T8	5
valid_sources[0x3d]	25944	1			T3	2		T4	13		T5	4
valid_sources[0x3e]	27855	1			T3	1		T4	25		T5	7
valid_sources[0x3f]	24667	1			T4	13		T5	2		T8	6
valid_sources[0x40]	26356	1			T4	21		T8	7		T11	4
valid_sources[0x41]	28971	1			T1	5		T4	18		T8	6
valid_sources[0x42]	27252	1			T4	14		T8	10		T10	13
valid_sources[0x43]	28133	1			T4	16		T5	5		T8	10
valid_sources[0x44]	28048	1			T4	7		T5	5		T8	14
valid_sources[0x45]	27572	1			T1	12		T3	1		T4	3
valid_sources[0x46]	32355	1			T1	9		T4	7		T8	4
valid_sources[0x47]	30305	1			T4	12		T8	8		T10	2
valid_sources[0x48]	30067	1			T4	2		T5	9		T8	12
valid_sources[0x49]	28301	1			T1	5		T4	21		T5	1
valid_sources[0x4a]	30312	1			T3	1		T4	10		T5	4
valid_sources[0x4b]	35371	1			T4	11		T5	5		T8	8
valid_sources[0x4c]	30074	1			T4	10		T5	4		T8	5
valid_sources[0x4d]	26730	1			T1	2		T4	18		T8	6
valid_sources[0x4e]	45492	1			T1	9		T4	9		T5	1
valid_sources[0x4f]	24914	1			T2	1		T3	1		T4	2
valid_sources[0x50]	27541	1			T4	16		T5	6		T8	9
valid_sources[0x51]	26257	1			T4	17		T5	4		T8	4
valid_sources[0x52]	26860	1			T4	16		T8	11		T10	4
valid_sources[0x53]	25511	1			T4	16		T5	1		T8	13
valid_sources[0x54]	29134	1			T4	20		T5	8		T8	9
valid_sources[0x55]	31125	1			T1	10		T4	24		T8	5
valid_sources[0x56]	29434	1			T1	4		T2	2		T4	20
valid_sources[0x57]	29002	1			T4	5		T5	9		T8	11
valid_sources[0x58]	27712	1			T1	21		T4	18		T8	11
valid_sources[0x59]	29438	1			T4	19		T8	6		T11	3
valid_sources[0x5a]	28981	1			T1	1		T4	13		T5	4
valid_sources[0x5b]	26689	1			T4	8		T5	4		T8	11
valid_sources[0x5c]	28977	1			T4	20		T5	4		T8	7
valid_sources[0x5d]	30663	1			T3	1		T4	10		T5	3
valid_sources[0x5e]	29968	1			T4	14		T8	6		T9	3
valid_sources[0x5f]	31446	1			T4	22		T5	3		T8	8
valid_sources[0x60]	29258	1			T2	1		T4	4		T5	3
valid_sources[0x61]	28593	1			T1	2		T4	6		T5	5
valid_sources[0x62]	26689	1			T1	16		T4	18		T5	4
valid_sources[0x63]	26376	1			T4	8		T5	7		T8	7
valid_sources[0x64]	29493	1			T4	8		T8	12		T10	2
valid_sources[0x65]	28748	1			T4	7		T5	6		T8	6
valid_sources[0x66]	28217	1			T4	13		T5	4		T8	10
valid_sources[0x67]	28138	1			T1	2		T4	22		T8	16
valid_sources[0x68]	31157	1			T1	3		T4	17		T5	5
valid_sources[0x69]	29120	1			T4	11		T5	4		T8	4
valid_sources[0x6a]	33656	1			T4	10		T8	7		T10	2
valid_sources[0x6b]	26929	1			T1	5		T8	5		T10	6
valid_sources[0x6c]	28997	1			T1	7		T4	11		T5	1
valid_sources[0x6d]	31759	1			T3	1		T4	23		T5	7
valid_sources[0x6e]	26585	1			T4	14		T8	7		T9	2
valid_sources[0x6f]	30673	1			T1	3		T4	14		T5	2
valid_sources[0x70]	30171	1			T1	2		T4	25		T8	3
valid_sources[0x71]	26199	1			T4	16		T5	5		T8	4
valid_sources[0x72]	27650	1			T4	18		T5	2		T8	9
valid_sources[0x73]	28076	1			T4	6		T5	1		T8	7
valid_sources[0x74]	30087	1			T4	18		T8	7		T9	3
valid_sources[0x75]	28074	1			T3	1		T4	11		T5	3
valid_sources[0x76]	28342	1			T4	12		T8	5		T10	9
valid_sources[0x77]	32037	1			T3	1		T4	8		T5	4
valid_sources[0x78]	30723	1			T4	19		T5	5		T8	3
valid_sources[0x79]	30484	1			T4	7		T8	10		T10	2
valid_sources[0x7a]	26206	1			T1	7		T4	6		T8	8
valid_sources[0x7b]	29238	1			T4	1		T8	15		T10	10
valid_sources[0x7c]	27987	1			T4	4		T5	10		T8	6
valid_sources[0x7d]	26323	1			T4	11		T5	4		T8	9
valid_sources[0x7e]	25344	1			T4	12		T5	6		T8	7
valid_sources[0x7f]	27185	1			T4	5		T5	5		T8	18
valid_sources[0x80]	29919	1			T1	33		T4	3		T8	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1079703

1

T1

1

T3

1

T4

1222

values[0x0]

all_enables

biggest_size

1528840

1

T1

216

T2

5

T3

8

values[0x1]

all_enables

biggest_size

1506620

1

T1

193

T2

4

T3

13