Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3231113

1

T1

88

T2

5

T3

7

full_word

4114408

1

T1

410

T2

9

T3

22

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7345161	1			T1	498		T2	14		T3	29
auto[TlIntgErrCmd]	135	1			T107	5		T108	4		T109	12
auto[TlIntgErrData]	99	1			T107	8		T108	3		T109	7
auto[TlIntgErrBoth]	126	1			T107	7		T108	3		T109	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3995540

1

T1

1

T2

1

T3

1

auto[1]

3349981

1

T1

497

T2

13

T3

28

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	2915451	1			T2	1		T4	1276		T7	5513
auto[TlIntgErrNone]	partial	auto[1]	315332	1			T1	88		T2	4		T3	7
auto[TlIntgErrNone]	full_word	auto[0]	1079924	1			T1	1		T3	1		T4	1222
auto[TlIntgErrNone]	full_word	auto[1]	3034454	1			T1	409		T2	9		T3	21
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T107	2		T108	1		T109	6
auto[TlIntgErrCmd]	partial	auto[1]	77	1			T107	2		T108	3		T109	4
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T107	1		T109	1		T201	2
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T109	1		T201	1		T202	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T107	4		T108	3		T109	3
auto[TlIntgErrData]	partial	auto[1]	37	1			T107	3		T109	3		T126	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T107	1		T109	1		T199	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T200	1		T203	1		T204	1
auto[TlIntgErrBoth]	partial	auto[0]	51	1			T107	2		T108	2		T109	5
auto[TlIntgErrBoth]	partial	auto[1]	68	1			T107	4		T108	1		T109	6
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T205	1		T201	1		T206	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T107	1		T201	1		T207	1