Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic 64.81 100.00 44.44 50.00
tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic 64.81 100.00 44.44 50.00
tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic 64.81 100.00 44.44 50.00
tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic 64.81 100.00 44.44 50.00
tb.dut.u_csb_rst_out_scan_mux.gen_generic.u_impl_generic 64.81 100.00 44.44 50.00
tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic 64.81 100.00 44.44 50.00
tb.dut.u_tpm_rst_out_scan_mux.gen_generic.u_impl_generic 64.81 100.00 44.44 50.00
tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 64.81 100.00 44.44 50.00
tb.dut.u_spid_status.u_csb_rst_scan_mux.gen_generic.u_impl_generic 64.81 100.00 44.44 50.00
tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic 85.19 100.00 55.56 100.00


Module Instance : tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_spi_in_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_spi_out_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_csb_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_csb_rst_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_csb_rst_out_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_csb_rst_out_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_tpm_csb_rst_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_tpm_rst_out_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_tpm_rst_out_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_spid_status.u_csb_rst_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_csb_rst_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3
Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
selKnown0 456587670 456580618 0 0
selKnown1 152067546 152066744 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 456587670 456580618 0 0
T1 167852 167849 0 0
T2 866 863 0 0
T3 2489 2486 0 0
T4 24927 24921 0 0
T5 263751 263745 0 0
T6 651 647 0 0
T7 102573 102567 0 0
T8 20025 20019 0 0
T9 240921 240917 0 0
T10 33405 33399 0 0
T11 7 4 0 0
T12 67 64 0 0
T13 48 70 0 0
T14 24 34 0 0
T15 28 40 0 0
T16 2 1 0 0
T17 0 2 0 0
T18 0 1 0 0
T19 0 1 0 0
T20 0 5 0 0
T21 0 2 0 0
T22 1 0 0 0
T23 1 0 0 0
T24 1 0 0 0
T25 1 0 0 0
T26 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 152067546 152066744 0 0
T1 55950 55949 0 0
T2 288 287 0 0
T3 829 828 0 0
T4 8302 8301 0 0
T5 87904 87903 0 0
T6 216 215 0 0
T7 34164 34163 0 0
T8 6658 6657 0 0
T9 80306 80305 0 0
T10 11126 11125 0 0

Line Coverage for Instance : tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3
Assert Coverage for Instance : tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 1 50.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 1 50.00 1 50.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
selKnown0 152067546 152066744 0 0
selKnown1 0 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 152067546 152066744 0 0
T1 55950 55949 0 0
T2 288 287 0 0
T3 829 828 0 0
T4 8302 8301 0 0
T5 87904 87903 0 0
T6 216 215 0 0
T7 34164 34163 0 0
T8 6658 6657 0 0
T9 80306 80305 0 0
T10 11126 11125 0 0

Line Coverage for Instance : tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3
Assert Coverage for Instance : tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 1 50.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 1 50.00 1 50.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
selKnown0 152068504 152067528 0 0
selKnown1 0 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 152068504 152067528 0 0
T1 55951 55950 0 0
T2 289 288 0 0
T3 830 829 0 0
T4 8303 8302 0 0
T5 87905 87904 0 0
T6 217 216 0 0
T7 34165 34164 0 0
T8 6659 6658 0 0
T9 80307 80306 0 0
T10 11127 11126 0 0

Line Coverage for Instance : tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT4,T5,T7
01CoveredT1,T2,T3
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T7
11CoveredT1,T2,T3
Assert Coverage for Instance : tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 1 50.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 1 50.00 1 50.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
selKnown0 63954 62978 0 0
selKnown1 0 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 63954 62978 0 0
T4 7 6 0 0
T5 13 12 0 0
T6 1 0 0 0
T7 27 26 0 0
T8 17 16 0 0
T9 1 0 0 0
T10 9 8 0 0
T11 3 2 0 0
T12 23 22 0 0
T13 0 24 0 0
T14 0 12 0 0
T15 0 14 0 0
T22 1 0 0 0

Line Coverage for Instance : tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T7
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT4,T5,T7
Assert Coverage for Instance : tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 1 50.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 1 50.00 1 50.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
selKnown0 62978 62305 0 0
selKnown1 0 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 62978 62305 0 0
T4 6 5 0 0
T5 12 11 0 0
T7 26 25 0 0
T8 16 15 0 0
T10 8 7 0 0
T11 2 1 0 0
T12 22 21 0 0
T13 24 23 0 0
T14 12 11 0 0
T15 14 13 0 0

Line Coverage for Instance : tb.dut.u_csb_rst_out_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_csb_rst_out_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T7
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT4,T5,T7
Assert Coverage for Instance : tb.dut.u_csb_rst_out_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 1 50.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 1 50.00 1 50.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
selKnown0 62048 61439 0 0
selKnown1 0 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 62048 61439 0 0
T4 6 5 0 0
T5 12 11 0 0
T7 26 25 0 0
T8 16 15 0 0
T10 8 7 0 0
T11 2 1 0 0
T12 22 21 0 0
T13 24 23 0 0
T14 12 11 0 0
T15 14 13 0 0

Line Coverage for Instance : tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3
Assert Coverage for Instance : tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 1 50.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 1 50.00 1 50.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
selKnown0 64613 64237 0 0
selKnown1 0 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 64613 64237 0 0
T1 251 250 0 0
T2 4 3 0 0
T3 9 8 0 0
T6 3 2 0 0
T9 334 333 0 0
T22 10 9 0 0
T27 13 12 0 0
T28 10 9 0 0
T29 4 3 0 0
T30 600 599 0 0

Line Coverage for Instance : tb.dut.u_tpm_rst_out_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_tpm_rst_out_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3
Assert Coverage for Instance : tb.dut.u_tpm_rst_out_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 1 50.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 1 50.00 1 50.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
selKnown0 63690 63378 0 0
selKnown1 0 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 63690 63378 0 0
T1 251 250 0 0
T2 4 3 0 0
T3 9 8 0 0
T6 3 2 0 0
T9 334 333 0 0
T22 10 9 0 0
T27 13 12 0 0
T29 4 3 0 0
T30 600 599 0 0
T31 21 20 0 0

Line Coverage for Instance : tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3
Assert Coverage for Instance : tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 1 50.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 1 50.00 1 50.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
selKnown0 64613 64237 0 0
selKnown1 0 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 64613 64237 0 0
T1 251 250 0 0
T2 4 3 0 0
T3 9 8 0 0
T6 3 2 0 0
T9 334 333 0 0
T22 10 9 0 0
T27 13 12 0 0
T28 10 9 0 0
T29 4 3 0 0
T30 600 599 0 0

Line Coverage for Instance : tb.dut.u_spid_status.u_csb_rst_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_spid_status.u_csb_rst_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3
Assert Coverage for Instance : tb.dut.u_spid_status.u_csb_rst_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 1 50.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 1 50.00 1 50.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
selKnown0 1220 244 0 0
selKnown1 0 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1220 244 0 0
T16 2 1 0 0
T17 0 2 0 0
T18 0 1 0 0
T19 0 1 0 0
T20 0 5 0 0
T21 0 2 0 0
T23 1 0 0 0
T24 1 0 0 0
T25 1 0 0 0
T26 1 0 0 0
T32 0 2 0 0
T33 0 2 0 0
T34 0 3 0 0
T35 0 1 0 0
T36 1 0 0 0
T37 1 0 0 0
T38 1 0 0 0
T39 1 0 0 0
T40 1 0 0 0

Line Coverage for Instance : tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3
Assert Coverage for Instance : tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
selKnown0 152068504 152067528 0 0
selKnown1 152067546 152066744 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 152068504 152067528 0 0
T1 55951 55950 0 0
T2 289 288 0 0
T3 830 829 0 0
T4 8303 8302 0 0
T5 87905 87904 0 0
T6 217 216 0 0
T7 34165 34164 0 0
T8 6659 6658 0 0
T9 80307 80306 0 0
T10 11127 11126 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 152067546 152066744 0 0
T1 55950 55949 0 0
T2 288 287 0 0
T3 829 828 0 0
T4 8302 8301 0 0
T5 87904 87903 0 0
T6 216 215 0 0
T7 34164 34163 0 0
T8 6658 6657 0 0
T9 80306 80305 0 0
T10 11126 11125 0 0