Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	459473188	2852666	0	0
DepthKnown_A	459473188	459339782	0	0
RvalidKnown_A	459473188	459339782	0	0
WreadyKnown_A	459473188	459339782	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459473188	2852666	0	0
T4	58997	832	0	0
T5	618215	1663	0	0
T6	2614	0	0	0
T7	280316	832	0	0
T8	23892	1672	0	0
T9	51346	0	0	0
T10	38390	1663	0	0
T11	11591	832	0	0
T12	12007	1670	0	0
T13	0	1663	0	0
T14	0	1663	0	0
T15	0	1663	0	0
T22	2571	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459473188	459339782	0	0
T1	332814	332748	0	0
T2	2184	2110	0	0
T3	7460	7362	0	0
T4	58997	58937	0	0
T5	618215	618157	0	0
T6	2614	2525	0	0
T7	280316	280238	0	0
T8	23892	23809	0	0
T9	51346	51283	0	0
T10	38390	38294	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459473188	459339782	0	0
T1	332814	332748	0	0
T2	2184	2110	0	0
T3	7460	7362	0	0
T4	58997	58937	0	0
T5	618215	618157	0	0
T6	2614	2525	0	0
T7	280316	280238	0	0
T8	23892	23809	0	0
T9	51346	51283	0	0
T10	38390	38294	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459473188	459339782	0	0
T1	332814	332748	0	0
T2	2184	2110	0	0
T3	7460	7362	0	0
T4	58997	58937	0	0
T5	618215	618157	0	0
T6	2614	2525	0	0
T7	280316	280238	0	0
T8	23892	23809	0	0
T9	51346	51283	0	0
T10	38390	38294	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	459473188	3216244	0	0
DepthKnown_A	459473188	459339782	0	0
RvalidKnown_A	459473188	459339782	0	0
WreadyKnown_A	459473188	459339782	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459473188	3216244	0	0
T4	58997	2551	0	0
T5	618215	832	0	0
T6	2614	0	0	0
T7	280316	2476	0	0
T8	23892	841	0	0
T9	51346	0	0	0
T10	38390	832	0	0
T11	11591	832	0	0
T12	12007	839	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	0	832	0	0
T22	2571	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459473188	459339782	0	0
T1	332814	332748	0	0
T2	2184	2110	0	0
T3	7460	7362	0	0
T4	58997	58937	0	0
T5	618215	618157	0	0
T6	2614	2525	0	0
T7	280316	280238	0	0
T8	23892	23809	0	0
T9	51346	51283	0	0
T10	38390	38294	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459473188	459339782	0	0
T1	332814	332748	0	0
T2	2184	2110	0	0
T3	7460	7362	0	0
T4	58997	58937	0	0
T5	618215	618157	0	0
T6	2614	2525	0	0
T7	280316	280238	0	0
T8	23892	23809	0	0
T9	51346	51283	0	0
T10	38390	38294	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459473188	459339782	0	0
T1	332814	332748	0	0
T2	2184	2110	0	0
T3	7460	7362	0	0
T4	58997	58937	0	0
T5	618215	618157	0	0
T6	2614	2525	0	0
T7	280316	280238	0	0
T8	23892	23809	0	0
T9	51346	51283	0	0
T10	38390	38294	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	459473188	195291	0	0
DepthKnown_A	459473188	459339782	0	0
RvalidKnown_A	459473188	459339782	0	0
WreadyKnown_A	459473188	459339782	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459473188	195291	0	0
T15	21196	0	0	0
T16	276480	2457	0	0
T23	0	1181	0	0
T25	0	100	0	0
T26	0	363	0	0
T27	18330	28	0	0
T28	917	0	0	0
T29	3054	1	0	0
T30	955672	1193	0	0
T31	73778	256	0	0
T37	0	959	0	0
T41	39560	0	0	0
T42	95382	310	0	0
T49	89474	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459473188	459339782	0	0
T1	332814	332748	0	0
T2	2184	2110	0	0
T3	7460	7362	0	0
T4	58997	58937	0	0
T5	618215	618157	0	0
T6	2614	2525	0	0
T7	280316	280238	0	0
T8	23892	23809	0	0
T9	51346	51283	0	0
T10	38390	38294	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459473188	459339782	0	0
T1	332814	332748	0	0
T2	2184	2110	0	0
T3	7460	7362	0	0
T4	58997	58937	0	0
T5	618215	618157	0	0
T6	2614	2525	0	0
T7	280316	280238	0	0
T8	23892	23809	0	0
T9	51346	51283	0	0
T10	38390	38294	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459473188	459339782	0	0
T1	332814	332748	0	0
T2	2184	2110	0	0
T3	7460	7362	0	0
T4	58997	58937	0	0
T5	618215	618157	0	0
T6	2614	2525	0	0
T7	280316	280238	0	0
T8	23892	23809	0	0
T9	51346	51283	0	0
T10	38390	38294	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	459473188	442996	0	0
DepthKnown_A	459473188	459339782	0	0
RvalidKnown_A	459473188	459339782	0	0
WreadyKnown_A	459473188	459339782	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459473188	442996	0	0
T15	21196	0	0	0
T16	276480	2456	0	0
T23	0	1181	0	0
T25	0	445	0	0
T26	0	363	0	0
T27	18330	28	0	0
T28	917	0	0	0
T29	3054	1	0	0
T30	955672	1193	0	0
T31	73778	256	0	0
T37	0	959	0	0
T41	39560	0	0	0
T42	95382	310	0	0
T49	89474	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459473188	459339782	0	0
T1	332814	332748	0	0
T2	2184	2110	0	0
T3	7460	7362	0	0
T4	58997	58937	0	0
T5	618215	618157	0	0
T6	2614	2525	0	0
T7	280316	280238	0	0
T8	23892	23809	0	0
T9	51346	51283	0	0
T10	38390	38294	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459473188	459339782	0	0
T1	332814	332748	0	0
T2	2184	2110	0	0
T3	7460	7362	0	0
T4	58997	58937	0	0
T5	618215	618157	0	0
T6	2614	2525	0	0
T7	280316	280238	0	0
T8	23892	23809	0	0
T9	51346	51283	0	0
T10	38390	38294	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459473188	459339782	0	0
T1	332814	332748	0	0
T2	2184	2110	0	0
T3	7460	7362	0	0
T4	58997	58937	0	0
T5	618215	618157	0	0
T6	2614	2525	0	0
T7	280316	280238	0	0
T8	23892	23809	0	0
T9	51346	51283	0	0
T10	38390	38294	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	459473188	5656886	0	0
DepthKnown_A	459473188	459339782	0	0
RvalidKnown_A	459473188	459339782	0	0
WreadyKnown_A	459473188	459339782	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459473188	5656886	0	0
T1	332814	498	0	0
T2	2184	14	0	0
T3	7460	29	0	0
T4	58997	2555	0	0
T5	618215	55	0	0
T6	2614	11	0	0
T7	280316	11147	0	0
T8	23892	1035	0	0
T9	51346	230	0	0
T10	38390	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459473188	459339782	0	0
T1	332814	332748	0	0
T2	2184	2110	0	0
T3	7460	7362	0	0
T4	58997	58937	0	0
T5	618215	618157	0	0
T6	2614	2525	0	0
T7	280316	280238	0	0
T8	23892	23809	0	0
T9	51346	51283	0	0
T10	38390	38294	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459473188	459339782	0	0
T1	332814	332748	0	0
T2	2184	2110	0	0
T3	7460	7362	0	0
T4	58997	58937	0	0
T5	618215	618157	0	0
T6	2614	2525	0	0
T7	280316	280238	0	0
T8	23892	23809	0	0
T9	51346	51283	0	0
T10	38390	38294	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459473188	459339782	0	0
T1	332814	332748	0	0
T2	2184	2110	0	0
T3	7460	7362	0	0
T4	58997	58937	0	0
T5	618215	618157	0	0
T6	2614	2525	0	0
T7	280316	280238	0	0
T8	23892	23809	0	0
T9	51346	51283	0	0
T10	38390	38294	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	459473188	12069188	0	0
DepthKnown_A	459473188	459339782	0	0
RvalidKnown_A	459473188	459339782	0	0
WreadyKnown_A	459473188	459339782	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459473188	12069188	0	0
T1	332814	2315	0	0
T2	2184	42	0	0
T3	7460	29	0	0
T4	58997	7799	0	0
T5	618215	55	0	0
T6	2614	59	0	0
T7	280316	34014	0	0
T8	23892	4389	0	0
T9	51346	230	0	0
T10	38390	145	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459473188	459339782	0	0
T1	332814	332748	0	0
T2	2184	2110	0	0
T3	7460	7362	0	0
T4	58997	58937	0	0
T5	618215	618157	0	0
T6	2614	2525	0	0
T7	280316	280238	0	0
T8	23892	23809	0	0
T9	51346	51283	0	0
T10	38390	38294	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459473188	459339782	0	0
T1	332814	332748	0	0
T2	2184	2110	0	0
T3	7460	7362	0	0
T4	58997	58937	0	0
T5	618215	618157	0	0
T6	2614	2525	0	0
T7	280316	280238	0	0
T8	23892	23809	0	0
T9	51346	51283	0	0
T10	38390	38294	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459473188	459339782	0	0
T1	332814	332748	0	0
T2	2184	2110	0	0
T3	7460	7362	0	0
T4	58997	58937	0	0
T5	618215	618157	0	0
T6	2614	2525	0	0
T7	280316	280238	0	0
T8	23892	23809	0	0
T9	51346	51283	0	0
T10	38390	38294	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0