Unified Coverage Report :: Module :: spi_passthrough

Module : spi_passthrough

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.17	94.50	88.66		75.00	92.71	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_passthrough.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_passthrough	90.17	94.50	88.66		75.00	92.71	100.00

---

Module Instance : tb.dut.u_passthrough

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.17	94.50	88.66		75.00	92.71	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.54	94.95	89.22		75.00	93.52	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_pt_sck_cg	100.00	100.00	100.00			100.00
u_read_half_cycle	100.00	100.00				100.00
u_read_pipe_oe_stg1	100.00	100.00				100.00
u_read_pipe_oe_stg2	100.00	100.00				100.00
u_read_pipe_stg1	100.00	100.00				100.00
u_read_pipe_stg2	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_passthrough

	Line No.	Total	Covered	Percent
TOTAL		200	189	94.50
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	333	1	1	100.00
ALWAYS	336	4	4	100.00
ALWAYS	345	4	4	100.00
ALWAYS	349	3	3	100.00
CONT_ASSIGN	355	1	1	100.00
ALWAYS	360	4	4	100.00
CONT_ASSIGN	372	1	1	100.00
CONT_ASSIGN	373	1	1	100.00
ALWAYS	376	4	4	100.00
ALWAYS	400	8	8	100.00
ALWAYS	414	4	4	100.00
ALWAYS	425	4	4	100.00
CONT_ASSIGN	439	0	0
ALWAYS	449	4	4	100.00
CONT_ASSIGN	463	1	1	100.00
ALWAYS	466	3	3	100.00
CONT_ASSIGN	475	1	1	100.00
ALWAYS	478	3	3	100.00
ALWAYS	486	6	6	100.00
CONT_ASSIGN	497	1	1	100.00
ALWAYS	506	3	3	100.00
ALWAYS	520	4	4	100.00
ALWAYS	528	3	3	100.00
ALWAYS	533	6	6	100.00
ALWAYS	539	3	3	100.00
CONT_ASSIGN	543	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
ALWAYS	561	5	5	100.00
CONT_ASSIGN	570	1	1	100.00
CONT_ASSIGN	572	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
CONT_ASSIGN	576	1	1	100.00
ALWAYS	582	6	6	100.00
CONT_ASSIGN	589	1	1	100.00
ALWAYS	596	6	4	66.67
CONT_ASSIGN	604	1	1	100.00
CONT_ASSIGN	609	1	1	100.00
ALWAYS	613	3	3	100.00
CONT_ASSIGN	616	1	1	100.00
ALWAYS	685	13	13	100.00
ALWAYS	713	3	3	100.00
CONT_ASSIGN	728	1	1	100.00
CONT_ASSIGN	734	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
ALWAYS	745	3	3	100.00
ALWAYS	753	68	59	86.76

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_passthrough.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_passthrough.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
271	1	1
276	1	1
326	1	1
333	1	1
336	1	1
337	1	1
338	1	1
339	1	1
			MISSING_ELSE
345	2	2
346	2	2
			MISSING_ELSE
349	2	2
350	1	1
355	1	1
360	1	1
361	1	1
362	1	1
363	1	1
			MISSING_ELSE
372	1	1
373	1	1
376	1	1
377	1	1
378	1	1
386	1	1
			MISSING_ELSE
400	1	1
401	1	1
402	1	1
403	1	1
404	1	1
405	1	1
406	1	1
407	1	1
			MISSING_ELSE
			MISSING_ELSE
			MISSING_ELSE
414	1	1
415	1	1
416	1	1
419	1	1
			MISSING_ELSE
425	1	1
426	1	1
427	1	1
430	1	1
			MISSING_ELSE
439		unreachable
449	1	1
451	1	1
454	1	1
456	1	1
			MISSING_ELSE
463	1	1
466	1	1
467	1	1
468	1	1
			MISSING_ELSE
475	1	1
478	1	1
479	1	1
481	1	1
486	1	1
487	1	1
488	1	1
489	1	1
490	1	1
491	1	1
			MISSING_ELSE
497	1	1
506	2	2
507	1	1
520	1	1
521	1	1
522	1	1
523	1	1
			MISSING_ELSE
528	2	2
529	1	1
533	2	2
534	2	2
535	2	2
			MISSING_ELSE
539	2	2
540	1	1
543	1	1
546	1	1
561	1	1
562	1	1
563	1	1
565	1	1
566	1	1
570	1	1
572	1	1
575	1	1
576	1	1
582	2	2
583	1	1
584	1	1
585	1	1
586	1	1
			MISSING_ELSE
589	1	1
596	1	1
597	1	1
598	1	1
599	0	1
600	1	1
601	0	1
			MISSING_ELSE
604	1	1
609	1	1
613	2	2
614	1	1
616	1	1
685	1	1
686	1	1
687	1	1
689	1	1
690	1	1
691	1	1
693	1	1
695	1	1
696	1	1
697	1	1
700	1	1
701	1	1
702	1	1
713	2	2
714	1	1
728	1	1
734	1	1
737	1	1
745	1	1
746	1	1
748	1	1
753	1	1
756	1	1
759	1	1
762	1	1
765	1	1
768	1	1
771	1	1
772	1	1
775	1	1
776	1	1
778	1	1
780	1	1
781	1	1
782	1	1
783	1	1
784	1	1
787	1	1
788	1	1
798	1	1
799	1	1
801	1	1
802	1	1
803	1	1
805	1	1
806	1	1
807	1	1
809	1	1
810	1	1
812	1	1
814	1	1
			MISSING_ELSE
818	1	1
820	1	1
821	1	1
			MISSING_ELSE
826	0	1
827	0	1
829	0	1
830	0	1
832	0	1
838	1	1
839	1	1
840	1	1
845	1	1
848	1	1
849	1	1
854	1	1
857	1	1
858	1	1
862	1	1
863	1	1
864	1	1
866	1	1
867	1	1
868	0	1
870	0	1
			MISSING_ELSE
876	1	1
877	1	1
878	0	1
880	0	1
881	1	1
882	1	1
884	1	1
885	1	1
886	1	1
888	1	1
889	1	1
891	1	1
893	1	1
896	1	1
			MISSING_ELSE

---

Cond Coverage for Module : spi_passthrough

	Total	Covered	Percent
Conditions	97	86	88.66
Logical	97	86	88.66
Non-Logical	0	0
Event	0	0

 LINE       271
 EXPRESSION (spi_mode_i == PassThrough)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       355
 SUB-EXPRESSION (filter | csb_deassert)
                 ---1--   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7

 LINE       362
 EXPRESSION (bitcnt != '1)
            -------1------

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T4,T5,T7

 LINE       372
 EXPRESSION (bitcnt == 6'(6))
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       373
 EXPRESSION (bitcnt == 6'(7))
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       404
 EXPRESSION (cmd_info_i[i].opcode == {opcode_d[6:0], 1'b1})
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T4,T5,T7

 LINE       406
 EXPRESSION (cmd_info_i[i].opcode == {opcode_d[6:0], 1'b0})
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T4,T5,T7

 LINE       467
 EXPRESSION (addr_mode == Addr4B)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T10

 LINE       475
 EXPRESSION (st == StAddress)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T10

 LINE       490
 EXPRESSION (addrcnt_outclk != '0)
            -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T5,T7,T10

 LINE       497
 EXPRESSION (cfg_addr_mask_i[addrcnt_outclk] ? cfg_addr_value_i[addrcnt_outclk] : host_s_i[0])
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       522
 EXPRESSION ((payloadcnt != '0) && payload_replace)
             ---------1--------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T14,T49
1	0	Covered	T4,T5,T7
1	1	Covered	T5,T14,T49

 LINE       522
 SUB-EXPRESSION (payloadcnt != '0)
                ---------1--------

-1-	Status	Tests
0	Covered	T5,T14,T49
1	Covered	T4,T5,T7

 LINE       543
 EXPRESSION (payloadcnt == '0)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T14,T49

 LINE       546
 EXPRESSION (cfg_payload_mask_i[payloadcnt_outclk] ? cfg_payload_data_i[payloadcnt_outclk] : host_s_i[0])
             ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       570
 EXPRESSION (addr_phase_outclk & cmd_info_addr_swap_en_outclk)
             --------1--------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T11,T49
1	0	Covered	T7,T10,T14
1	1	Covered	T5,T11,T49

 LINE       572
 EXPRESSION (payload_replace_outclk & cmd_info_payload_swap_en_outclk)
             -----------1----------   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T49,T42
1	0	Covered	T4,T8,T12
1	1	Covered	T5,T49,T42

 LINE       575
 EXPRESSION (addr_swap_en | payload_swap_en)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T49,T42
1	0	Covered	T5,T11,T49

 LINE       576
 EXPRESSION (addr_swap_en ? addr_swap : payload_swap)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T11,T49

 LINE       585
 EXPRESSION (st == StHighZ)
            -------1-------

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T5,T7,T10

 LINE       589
 EXPRESSION (dummycnt == '0)
            --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       600
 EXPRESSION (st == StMByte)
            -------1-------

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Not Covered

 LINE       604
 EXPRESSION (mbyte_cnt == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       609
 EXPRESSION (swap_en ? ({host_s_i[3:1], swap_data}) : host_s_i)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T11,T49

 LINE       734
 EXPRESSION (host_csb_i | csb_deassert_outclk)
             -----1----   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T7
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T2,T3

 LINE       737
 EXPRESSION (is_active && ((!passthrough_block_i)))
             ----1----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T42,T16,T23
1	1	Covered	T4,T5,T7

 LINE       782
 EXPRESSION (cmd_8th && cmd_filter[host_s_i[0]])
             ---1---    -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       787
 EXPRESSION (cmd_8th && cmd_info_d.valid)
             ---1---    --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       798
 EXPRESSION (cmd_info_d.addr_mode != AddrDisabled)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T5,T7,T10

 LINE       807
 EXPRESSION (cmd_info_d.payload_en != 4'b0)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T16,T23,T26
1	Covered	T4,T5,T7

 LINE       809
 EXPRESSION (cmd_info_d.payload_dir == PayloadOut)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T4,T8,T12
1	Covered	T5,T7,T13

 LINE       864
 EXPRESSION (dummycnt_zero && (cmd_info.payload_dir == PayloadOut))
             ------1------    ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T10
1	0	Not Covered
1	1	Covered	T5,T7,T10

 LINE       864
 SUB-EXPRESSION (cmd_info.payload_dir == PayloadOut)
                ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Covered	T5,T7,T10

 LINE       867
 EXPRESSION (dummycnt_zero && (cmd_info.payload_dir == PayloadIn))
             ------1------    -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       867
 SUB-EXPRESSION (cmd_info.payload_dir == PayloadIn)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T5,T7,T10
1	Not Covered

 LINE       876
 EXPRESSION (addrcnt_outclk == '0)
            -----------1----------

-1-	Status	Tests
0	Covered	T5,T7,T10
1	Covered	T5,T7,T10

 LINE       886
 EXPRESSION ((cmd_info.payload_en != 4'b0) && (cmd_info.payload_dir == PayloadOut))
             --------------1--------------    ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T42,T16,T23
1	0	Covered	T5,T14,T42
1	1	Covered	T7,T16,T23

 LINE       886
 SUB-EXPRESSION (cmd_info.payload_en != 4'b0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T42,T16,T23
1	Covered	T5,T7,T14

 LINE       886
 SUB-EXPRESSION (cmd_info.payload_dir == PayloadOut)
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T5,T14,T42
1	Covered	T7,T42,T16

 LINE       889
 EXPRESSION ((cmd_info.payload_en != 4'b0) && (cmd_info.payload_dir == PayloadIn))
             --------------1--------------    -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T5,T14,T42

 LINE       889
 SUB-EXPRESSION (cmd_info.payload_en != 4'b0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T42,T16,T23
1	Covered	T5,T14,T42

 LINE       889
 SUB-EXPRESSION (cmd_info.payload_dir == PayloadIn)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T42,T16,T23
1	Covered	T5,T14,T42

---

FSM Coverage for Module : spi_passthrough

Summary for FSM :: st

	Total	Covered	Percent
States	7	6	85.71	(Not included in score)
Transitions	12	9	75.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StAddress	799	Covered	T5,T7,T10
StDriving	812	Covered	T4,T5,T8
StFilter	783	Covered	T4,T5,T7
StHighZ	803	Covered	T5,T7,T10
StIdle	781	Covered	T1,T2,T3
StMByte	832	Not Covered
StWait	810	Covered	T5,T7,T10

transitions	Line No.	Covered	Tests
StAddress->StDriving	891	Covered	T5,T14,T42
StAddress->StHighZ	882	Covered	T5,T7,T10
StAddress->StMByte	878	Not Covered
StAddress->StWait	888	Covered	T7,T42,T16
StHighZ->StDriving	868	Not Covered
StHighZ->StWait	866	Covered	T5,T7,T10
StIdle->StAddress	799	Covered	T5,T7,T10
StIdle->StDriving	812	Covered	T4,T8,T12
StIdle->StFilter	783	Covered	T4,T5,T7
StIdle->StHighZ	803	Covered	T42,T16,T23
StIdle->StWait	810	Covered	T5,T7,T13
StMByte->StHighZ	827	Not Covered

---

Branch Coverage for Module : spi_passthrough

	Line No.	Total	Covered	Percent
Branches		96	89	92.71
TERNARY	497	2	2	100.00
TERNARY	546	2	2	100.00
TERNARY	576	2	2	100.00
TERNARY	609	2	2	100.00
IF	336	3	3	100.00
IF	345	3	3	100.00
IF	349	2	2	100.00
IF	360	3	3	100.00
IF	376	3	3	100.00
IF	401	2	2	100.00
IF	414	3	3	100.00
IF	425	3	3	100.00
IF	451	2	2	100.00
IF	467	2	2	100.00
IF	478	2	2	100.00
IF	486	4	4	100.00
IF	506	2	2	100.00
IF	520	3	3	100.00
IF	528	2	2	100.00
IF	533	4	4	100.00
IF	539	2	2	100.00
IF	561	2	2	100.00
IF	582	4	4	100.00
IF	596	4	2	50.00
IF	613	2	2	100.00
CASE	693	3	3	100.00
IF	713	2	2	100.00
IF	745	2	2	100.00
CASE	778	24	19	79.17

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_passthrough.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_passthrough.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	497	(cfg_addr_mask_i[addrcnt_outclk]) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	546	(cfg_payload_mask_i[payloadcnt_outclk]) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	576	(addr_swap_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T11,T49
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	609	(swap_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T11,T49
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	336	if ((!rst_ni))
-2-:	338	if ((bitcnt < 6'(8)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
0	0	Covered	T4,T5,T7

	LineNo.	Expression
-1-:	345	if ((!rst_ni))
-2-:	346	if (filter)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
0	0	Covered	T4,T5,T7

	LineNo.	Expression
-1-:	349	if ((!rst_out_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

	LineNo.	Expression
-1-:	360	if ((!rst_ni))
-2-:	362	if ((bitcnt != '1))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
0	0	Covered	T4,T5,T7

	LineNo.	Expression
-1-:	376	if ((!rst_ni))
-2-:	378	if (cmd_7th)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
0	0	Covered	T4,T5,T7

	LineNo.	Expression
-1-:	401	if (cmd_7th)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	414	if ((!rst_ni))
-2-:	416	if (cmd_7th)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
0	0	Covered	T4,T5,T7

	LineNo.	Expression
-1-:	425	if ((!rst_ni))
-2-:	427	if (cmd_info_latch)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
0	0	Covered	T4,T5,T7

	LineNo.	Expression
-1-:	451	if (cmd_8th)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	467	if ((addr_mode == Addr4B))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	478	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

	LineNo.	Expression
-1-:	486	if ((!rst_out_ni))
-2-:	488	if (addr_set_q)
-3-:	490	if ((addrcnt_outclk != '0))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T7,T10
0	0	1	Covered	T5,T7,T10
0	0	0	Covered	T4,T5,T7

	LineNo.	Expression
-1-:	506	if ((!rst_out_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

	LineNo.	Expression
-1-:	520	if ((!rst_ni))
-2-:	522	if (((payloadcnt != '0) && payload_replace))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T14,T49
0	0	Covered	T4,T5,T7

	LineNo.	Expression
-1-:	528	if ((!rst_out_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

	LineNo.	Expression
-1-:	533	if ((!rst_ni))
-2-:	534	if (payload_replace_set)
-3-:	535	if (payload_replace_clr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T8
0	0	1	Covered	T5,T14,T49
0	0	0	Covered	T4,T5,T7

	LineNo.	Expression
-1-:	539	if ((!rst_out_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

	LineNo.	Expression
-1-:	561	if ((!rst_out_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

	LineNo.	Expression
-1-:	582	if ((!rst_ni))
-2-:	583	if (dummy_set)
-3-:	585	if ((st == StHighZ))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T7,T10
0	0	1	Covered	T5,T7,T10
0	0	0	Covered	T4,T5,T7

	LineNo.	Expression
-1-:	596	if ((!rst_ni))
-2-:	598	if (mbyte_set)
-3-:	600	if ((st == StMByte))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T4,T5,T7

	LineNo.	Expression
-1-:	613	if ((!rst_out_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

	LineNo.	Expression
-1-:	693	case (cmd_info.read_pipeline_mode)

Branches:

-1-	Status	Tests
RdPipeTwoStageFullCycle	Covered	T5,T42,T16
RdPipeTwoStageHalfCycle	Covered	T7,T10,T49
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	713	if ((!rst_out_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

	LineNo.	Expression
-1-:	745	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

	LineNo.	Expression
-1-:	778	case (st)
-2-:	780	if ((!is_active))
-3-:	782	if ((cmd_8th && cmd_filter[host_s_i[0]]))
-4-:	787	if ((cmd_8th && cmd_info_d.valid))
-5-:	798	if ((cmd_info_d.addr_mode != AddrDisabled))
-6-:	802	if (cmd_info_d.dummy_en)
-7-:	807	if ((cmd_info_d.payload_en != 4'b0))
-8-:	809	if ((cmd_info_d.payload_dir == PayloadOut))
-9-:	818	if (cmd_8th)
-10-:	826	if (mbytecnt_zero)
-11-:	864	if ((dummycnt_zero && (cmd_info.payload_dir == PayloadOut)))
-12-:	867	if ((dummycnt_zero && (cmd_info.payload_dir == PayloadIn)))
-13-:	876	if ((addrcnt_outclk == '0))
-14-:	877	if (cmd_info.mbyte_en)
-15-:	881	if (cmd_info.dummy_en)
-16-:	886	if (((cmd_info.payload_en != 4'b0) && (cmd_info.payload_dir == PayloadOut)))
-17-:	889	if (((cmd_info.payload_en != 4'b0) && (cmd_info.payload_dir == PayloadIn)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T7
StIdle	0	0	1	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T7,T10
StIdle	0	0	1	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T42,T16
StIdle	0	0	1	0	0	1	1	-	-	-	-	-	-	-	-	-	Covered	T5,T7,T13
StIdle	0	0	1	0	0	1	0	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T12
StIdle	0	0	1	0	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T16,T23,T26
StIdle	0	0	0	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T5,T7
StIdle	0	0	0	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T4,T5,T7
StMByte	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Not Covered
StMByte	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
StFilter	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T7
StWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T7,T10
StDriving	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T8
StHighZ	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T7,T10
StHighZ	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	Not Covered
StHighZ	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T5,T7,T10
StAddress	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	Not Covered
StAddress	-	-	-	-	-	-	-	-	-	-	-	1	0	1	-	-	Covered	T5,T7,T10
StAddress	-	-	-	-	-	-	-	-	-	-	-	1	0	0	1	-	Covered	T7,T16,T23
StAddress	-	-	-	-	-	-	-	-	-	-	-	1	0	0	0	1	Covered	T5,T14,T42
StAddress	-	-	-	-	-	-	-	-	-	-	-	1	0	0	0	0	Covered	T42,T16,T23
StAddress	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T5,T7,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

---

Assert Coverage for Module : spi_passthrough

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PassThroughStKnown_A	152067546	123162524	0	0
PayloadSwapConstraint_M	152067546	2523104	0	0

PassThroughStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	123162524	0	0
T4	8302	8240	0	0
T5	87904	87904	0	0
T6	216	0	0	0
T7	34164	33734	0	0
T8	6658	6272	0	0
T9	80306	0	0	0
T10	11126	10910	0	0
T11	4427	4176	0	0
T12	10447	9920	0	0
T13	0	192256	0	0
T14	0	44912	0	0
T15	0	2800	0	0
T22	877	0	0	0

PayloadSwapConstraint_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	2523104	0	0
T5	87904	13128	0	0
T6	216	0	0	0
T7	34164	0	0	0
T8	6658	0	0	0
T9	80306	0	0	0
T10	11126	0	0	0
T11	4427	0	0	0
T12	10447	0	0	0
T13	192710	0	0	0
T16	0	25768	0	0
T17	0	33008	0	0
T22	877	0	0	0
T23	0	2160	0	0
T40	0	6040	0	0
T42	0	78104	0	0
T49	0	2048	0	0
T53	0	60160	0	0
T54	0	32	0	0
T55	0	34432	0	0