Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T27,T29,T30
1	0	Covered	T27,T29,T30

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T27,T29,T30

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T31,T42,T16

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T31,T42,T16
1	0	Covered	T31,T42,T16

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Unreachable
1	1	Covered	T31,T42,T16

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T27,T29,T30

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T27,T29,T30
1	0	Covered	T4,T5,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T4,T5,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T29,T30
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T7
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	761425358	607940085	0	0
CheckNGreaterZero_A	2928	2928	0	0
GntImpliesReady_A	761425358	3741262	0	0
GntImpliesValid_A	761425358	3741262	0	0
GrantKnown_A	761425358	607940085	0	0
IdxKnown_A	761425358	607940085	0	0
IndexIsCorrect_A	761425358	3741262	0	0
LockArbDecision_A	761425358	0	0	0
NoReadyValidNoGrant_A	761425358	0	0	0
ReadyAndValidImplyGrant_A	761425358	3741262	0	0
ReqAndReadyImplyGrant_A	761425358	3741262	0	0
ReqImpliesValid_A	761425358	3741262	0	0
ReqStaysHighUntilGranted0_M	761425358	0	0	0
RoundRobin_A	761425358	3	0	976
ValidKnown_A	761425358	607940085	0	0
gen_data_port_assertion.DataFlow_A	761425358	3741262	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761425358	607940085	0	0
T1	388764	386516	0	0
T2	2472	2398	0	0
T3	8289	8010	0	0
T4	75601	67177	0	0
T5	794023	706061	0	0
T6	3046	2741	0	0
T7	348644	313972	0	0
T8	37208	30081	0	0
T9	211958	127755	0	0
T10	60642	49204	0	0
T11	4427	4176	0	0
T12	10447	9920	0	0
T13	0	192256	0	0
T14	0	44912	0	0
T15	0	2800	0	0
T22	877	720	0	0
T27	0	1952	0	0
T29	0	280	0	0
T30	0	168912	0	0
T31	0	30056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2928	2928	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761425358	3741262	0	0
T4	58997	832	0	0
T5	618215	832	0	0
T6	2614	0	0	0
T7	280316	832	0	0
T8	23892	832	0	0
T9	51346	0	0	0
T10	38390	832	0	0
T11	11591	832	0	0
T12	12007	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	3191	0	0	0
T16	220464	18522	0	0
T22	2571	0	0	0
T23	216446	10888	0	0
T24	93090	0	0	0
T26	0	4455	0	0
T27	2430	175	0	0
T29	280	6	0	0
T30	179193	7215	0	0
T31	352052	1394	0	0
T37	0	5200	0	0
T40	0	4730	0	0
T41	11998	0	0	0
T42	513242	6413	0	0
T48	0	876	0	0
T49	78503	0	0	0
T56	0	188	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761425358	3741262	0	0
T4	58997	832	0	0
T5	618215	832	0	0
T6	2614	0	0	0
T7	280316	832	0	0
T8	23892	832	0	0
T9	51346	0	0	0
T10	38390	832	0	0
T11	11591	832	0	0
T12	12007	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	3191	0	0	0
T16	220464	18522	0	0
T22	2571	0	0	0
T23	216446	10888	0	0
T24	93090	0	0	0
T26	0	4455	0	0
T27	2430	175	0	0
T29	280	6	0	0
T30	179193	7215	0	0
T31	352052	1394	0	0
T37	0	5200	0	0
T40	0	4730	0	0
T41	11998	0	0	0
T42	513242	6413	0	0
T48	0	876	0	0
T49	78503	0	0	0
T56	0	188	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761425358	607940085	0	0
T1	388764	386516	0	0
T2	2472	2398	0	0
T3	8289	8010	0	0
T4	75601	67177	0	0
T5	794023	706061	0	0
T6	3046	2741	0	0
T7	348644	313972	0	0
T8	37208	30081	0	0
T9	211958	127755	0	0
T10	60642	49204	0	0
T11	4427	4176	0	0
T12	10447	9920	0	0
T13	0	192256	0	0
T14	0	44912	0	0
T15	0	2800	0	0
T22	877	720	0	0
T27	0	1952	0	0
T29	0	280	0	0
T30	0	168912	0	0
T31	0	30056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761425358	607940085	0	0
T1	388764	386516	0	0
T2	2472	2398	0	0
T3	8289	8010	0	0
T4	75601	67177	0	0
T5	794023	706061	0	0
T6	3046	2741	0	0
T7	348644	313972	0	0
T8	37208	30081	0	0
T9	211958	127755	0	0
T10	60642	49204	0	0
T11	4427	4176	0	0
T12	10447	9920	0	0
T13	0	192256	0	0
T14	0	44912	0	0
T15	0	2800	0	0
T22	877	720	0	0
T27	0	1952	0	0
T29	0	280	0	0
T30	0	168912	0	0
T31	0	30056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761425358	3741262	0	0
T4	58997	832	0	0
T5	618215	832	0	0
T6	2614	0	0	0
T7	280316	832	0	0
T8	23892	832	0	0
T9	51346	0	0	0
T10	38390	832	0	0
T11	11591	832	0	0
T12	12007	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	3191	0	0	0
T16	220464	18522	0	0
T22	2571	0	0	0
T23	216446	10888	0	0
T24	93090	0	0	0
T26	0	4455	0	0
T27	2430	175	0	0
T29	280	6	0	0
T30	179193	7215	0	0
T31	352052	1394	0	0
T37	0	5200	0	0
T40	0	4730	0	0
T41	11998	0	0	0
T42	513242	6413	0	0
T48	0	876	0	0
T49	78503	0	0	0
T56	0	188	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761425358	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761425358	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761425358	3741262	0	0
T4	58997	832	0	0
T5	618215	832	0	0
T6	2614	0	0	0
T7	280316	832	0	0
T8	23892	832	0	0
T9	51346	0	0	0
T10	38390	832	0	0
T11	11591	832	0	0
T12	12007	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	3191	0	0	0
T16	220464	18522	0	0
T22	2571	0	0	0
T23	216446	10888	0	0
T24	93090	0	0	0
T26	0	4455	0	0
T27	2430	175	0	0
T29	280	6	0	0
T30	179193	7215	0	0
T31	352052	1394	0	0
T37	0	5200	0	0
T40	0	4730	0	0
T41	11998	0	0	0
T42	513242	6413	0	0
T48	0	876	0	0
T49	78503	0	0	0
T56	0	188	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761425358	3741262	0	0
T4	58997	832	0	0
T5	618215	832	0	0
T6	2614	0	0	0
T7	280316	832	0	0
T8	23892	832	0	0
T9	51346	0	0	0
T10	38390	832	0	0
T11	11591	832	0	0
T12	12007	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	3191	0	0	0
T16	220464	18522	0	0
T22	2571	0	0	0
T23	216446	10888	0	0
T24	93090	0	0	0
T26	0	4455	0	0
T27	2430	175	0	0
T29	280	6	0	0
T30	179193	7215	0	0
T31	352052	1394	0	0
T37	0	5200	0	0
T40	0	4730	0	0
T41	11998	0	0	0
T42	513242	6413	0	0
T48	0	876	0	0
T49	78503	0	0	0
T56	0	188	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761425358	3741262	0	0
T4	58997	832	0	0
T5	618215	832	0	0
T6	2614	0	0	0
T7	280316	832	0	0
T8	23892	832	0	0
T9	51346	0	0	0
T10	38390	832	0	0
T11	11591	832	0	0
T12	12007	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	3191	0	0	0
T16	220464	18522	0	0
T22	2571	0	0	0
T23	216446	10888	0	0
T24	93090	0	0	0
T26	0	4455	0	0
T27	2430	175	0	0
T29	280	6	0	0
T30	179193	7215	0	0
T31	352052	1394	0	0
T37	0	5200	0	0
T40	0	4730	0	0
T41	11998	0	0	0
T42	513242	6413	0	0
T48	0	876	0	0
T49	78503	0	0	0
T56	0	188	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	761425358	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761425358	3	0	976
T35	169534	0	0	1
T44	0	1	0	0
T57	213976	1	0	1
T58	0	1	0	0
T59	156810	0	0	1
T60	668908	0	0	1
T61	104419	0	0	1
T62	6861	0	0	1
T63	242538	0	0	1
T64	147311	0	0	1
T65	9584	0	0	1
T66	55661	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761425358	607940085	0	0
T1	388764	386516	0	0
T2	2472	2398	0	0
T3	8289	8010	0	0
T4	75601	67177	0	0
T5	794023	706061	0	0
T6	3046	2741	0	0
T7	348644	313972	0	0
T8	37208	30081	0	0
T9	211958	127755	0	0
T10	60642	49204	0	0
T11	4427	4176	0	0
T12	10447	9920	0	0
T13	0	192256	0	0
T14	0	44912	0	0
T15	0	2800	0	0
T22	877	720	0	0
T27	0	1952	0	0
T29	0	280	0	0
T30	0	168912	0	0
T31	0	30056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761425358	3741262	0	0
T4	58997	832	0	0
T5	618215	832	0	0
T6	2614	0	0	0
T7	280316	832	0	0
T8	23892	832	0	0
T9	51346	0	0	0
T10	38390	832	0	0
T11	11591	832	0	0
T12	12007	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	3191	0	0	0
T16	220464	18522	0	0
T22	2571	0	0	0
T23	216446	10888	0	0
T24	93090	0	0	0
T26	0	4455	0	0
T27	2430	175	0	0
T29	280	6	0	0
T30	179193	7215	0	0
T31	352052	1394	0	0
T37	0	5200	0	0
T40	0	4730	0	0
T41	11998	0	0	0
T42	513242	6413	0	0
T48	0	876	0	0
T49	78503	0	0	0
T56	0	188	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T27,T29,T30
1	0	Covered	T27,T29,T30

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T27,T29,T30

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T27,T29,T30
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T27,T29,T30
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T27,T29,T30
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	152067546	27578874	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	152067546	615187	0	0
GntImpliesValid_A	152067546	615187	0	0
GrantKnown_A	152067546	27578874	0	0
IdxKnown_A	152067546	27578874	0	0
IndexIsCorrect_A	152067546	615187	0	0
LockArbDecision_A	152067546	0	0	0
NoReadyValidNoGrant_A	152067546	0	0	0
ReadyAndValidImplyGrant_A	152067546	615187	0	0
ReqAndReadyImplyGrant_A	152067546	615187	0	0
ReqImpliesValid_A	152067546	615187	0	0
ReqStaysHighUntilGranted0_M	152067546	0	0	0
RoundRobin_A	152067546	0	0	0
ValidKnown_A	152067546	27578874	0	0
gen_data_port_assertion.DataFlow_A	152067546	615187	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	27578874	0	0
T1	55950	53768	0	0
T2	288	288	0	0
T3	829	648	0	0
T4	8302	0	0	0
T5	87904	0	0	0
T6	216	216	0	0
T7	34164	0	0	0
T8	6658	0	0	0
T9	80306	76472	0	0
T10	11126	0	0	0
T22	0	720	0	0
T27	0	1952	0	0
T29	0	280	0	0
T30	0	168912	0	0
T31	0	30056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	615187	0	0
T15	3191	0	0	0
T16	110232	10874	0	0
T23	108223	3307	0	0
T26	0	1047	0	0
T27	2430	130	0	0
T29	280	6	0	0
T30	179193	7215	0	0
T31	176026	234	0	0
T37	0	5200	0	0
T40	0	4471	0	0
T41	11998	0	0	0
T42	256621	0	0	0
T49	78503	0	0	0
T56	0	188	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	615187	0	0
T15	3191	0	0	0
T16	110232	10874	0	0
T23	108223	3307	0	0
T26	0	1047	0	0
T27	2430	130	0	0
T29	280	6	0	0
T30	179193	7215	0	0
T31	176026	234	0	0
T37	0	5200	0	0
T40	0	4471	0	0
T41	11998	0	0	0
T42	256621	0	0	0
T49	78503	0	0	0
T56	0	188	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	27578874	0	0
T1	55950	53768	0	0
T2	288	288	0	0
T3	829	648	0	0
T4	8302	0	0	0
T5	87904	0	0	0
T6	216	216	0	0
T7	34164	0	0	0
T8	6658	0	0	0
T9	80306	76472	0	0
T10	11126	0	0	0
T22	0	720	0	0
T27	0	1952	0	0
T29	0	280	0	0
T30	0	168912	0	0
T31	0	30056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	27578874	0	0
T1	55950	53768	0	0
T2	288	288	0	0
T3	829	648	0	0
T4	8302	0	0	0
T5	87904	0	0	0
T6	216	216	0	0
T7	34164	0	0	0
T8	6658	0	0	0
T9	80306	76472	0	0
T10	11126	0	0	0
T22	0	720	0	0
T27	0	1952	0	0
T29	0	280	0	0
T30	0	168912	0	0
T31	0	30056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	615187	0	0
T15	3191	0	0	0
T16	110232	10874	0	0
T23	108223	3307	0	0
T26	0	1047	0	0
T27	2430	130	0	0
T29	280	6	0	0
T30	179193	7215	0	0
T31	176026	234	0	0
T37	0	5200	0	0
T40	0	4471	0	0
T41	11998	0	0	0
T42	256621	0	0	0
T49	78503	0	0	0
T56	0	188	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	615187	0	0
T15	3191	0	0	0
T16	110232	10874	0	0
T23	108223	3307	0	0
T26	0	1047	0	0
T27	2430	130	0	0
T29	280	6	0	0
T30	179193	7215	0	0
T31	176026	234	0	0
T37	0	5200	0	0
T40	0	4471	0	0
T41	11998	0	0	0
T42	256621	0	0	0
T49	78503	0	0	0
T56	0	188	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	615187	0	0
T15	3191	0	0	0
T16	110232	10874	0	0
T23	108223	3307	0	0
T26	0	1047	0	0
T27	2430	130	0	0
T29	280	6	0	0
T30	179193	7215	0	0
T31	176026	234	0	0
T37	0	5200	0	0
T40	0	4471	0	0
T41	11998	0	0	0
T42	256621	0	0	0
T49	78503	0	0	0
T56	0	188	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	615187	0	0
T15	3191	0	0	0
T16	110232	10874	0	0
T23	108223	3307	0	0
T26	0	1047	0	0
T27	2430	130	0	0
T29	280	6	0	0
T30	179193	7215	0	0
T31	176026	234	0	0
T37	0	5200	0	0
T40	0	4471	0	0
T41	11998	0	0	0
T42	256621	0	0	0
T49	78503	0	0	0
T56	0	188	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	27578874	0	0
T1	55950	53768	0	0
T2	288	288	0	0
T3	829	648	0	0
T4	8302	0	0	0
T5	87904	0	0	0
T6	216	216	0	0
T7	34164	0	0	0
T8	6658	0	0	0
T9	80306	76472	0	0
T10	11126	0	0	0
T22	0	720	0	0
T27	0	1952	0	0
T29	0	280	0	0
T30	0	168912	0	0
T31	0	30056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	615187	0	0
T15	3191	0	0	0
T16	110232	10874	0	0
T23	108223	3307	0	0
T26	0	1047	0	0
T27	2430	130	0	0
T29	280	6	0	0
T30	179193	7215	0	0
T31	176026	234	0	0
T37	0	5200	0	0
T40	0	4471	0	0
T41	11998	0	0	0
T42	256621	0	0	0
T49	78503	0	0	0
T56	0	188	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T31,T42,T16

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T31,T42,T16
1	0	Covered	T31,T42,T16

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Unreachable
1	1	Covered	T31,T42,T16

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T42,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T31,T42,T16
0	0	1	Unreachable
0	0	0	Covered	T4,T5,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T31,T42,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T31,T42,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	152067546	123162524	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	152067546	874117	0	0
GntImpliesValid_A	152067546	874117	0	0
GrantKnown_A	152067546	123162524	0	0
IdxKnown_A	152067546	123162524	0	0
IndexIsCorrect_A	152067546	874117	0	0
LockArbDecision_A	152067546	0	0	0
NoReadyValidNoGrant_A	152067546	0	0	0
ReadyAndValidImplyGrant_A	152067546	874117	0	0
ReqAndReadyImplyGrant_A	152067546	874117	0	0
ReqImpliesValid_A	152067546	874117	0	0
ReqStaysHighUntilGranted0_M	152067546	0	0	0
RoundRobin_A	152067546	0	0	0
ValidKnown_A	152067546	123162524	0	0
gen_data_port_assertion.DataFlow_A	152067546	874117	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	123162524	0	0
T4	8302	8240	0	0
T5	87904	87904	0	0
T6	216	0	0	0
T7	34164	33734	0	0
T8	6658	6272	0	0
T9	80306	0	0	0
T10	11126	10910	0	0
T11	4427	4176	0	0
T12	10447	9920	0	0
T13	0	192256	0	0
T14	0	44912	0	0
T15	0	2800	0	0
T22	877	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	874117	0	0
T16	110232	7648	0	0
T17	0	7391	0	0
T23	108223	7581	0	0
T24	93090	0	0	0
T26	601627	3408	0	0
T31	176026	1160	0	0
T36	53095	0	0	0
T37	146825	0	0	0
T39	65387	0	0	0
T40	385799	259	0	0
T42	256621	6413	0	0
T48	0	876	0	0
T67	0	132	0	0
T68	0	514	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	874117	0	0
T16	110232	7648	0	0
T17	0	7391	0	0
T23	108223	7581	0	0
T24	93090	0	0	0
T26	601627	3408	0	0
T31	176026	1160	0	0
T36	53095	0	0	0
T37	146825	0	0	0
T39	65387	0	0	0
T40	385799	259	0	0
T42	256621	6413	0	0
T48	0	876	0	0
T67	0	132	0	0
T68	0	514	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	123162524	0	0
T4	8302	8240	0	0
T5	87904	87904	0	0
T6	216	0	0	0
T7	34164	33734	0	0
T8	6658	6272	0	0
T9	80306	0	0	0
T10	11126	10910	0	0
T11	4427	4176	0	0
T12	10447	9920	0	0
T13	0	192256	0	0
T14	0	44912	0	0
T15	0	2800	0	0
T22	877	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	123162524	0	0
T4	8302	8240	0	0
T5	87904	87904	0	0
T6	216	0	0	0
T7	34164	33734	0	0
T8	6658	6272	0	0
T9	80306	0	0	0
T10	11126	10910	0	0
T11	4427	4176	0	0
T12	10447	9920	0	0
T13	0	192256	0	0
T14	0	44912	0	0
T15	0	2800	0	0
T22	877	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	874117	0	0
T16	110232	7648	0	0
T17	0	7391	0	0
T23	108223	7581	0	0
T24	93090	0	0	0
T26	601627	3408	0	0
T31	176026	1160	0	0
T36	53095	0	0	0
T37	146825	0	0	0
T39	65387	0	0	0
T40	385799	259	0	0
T42	256621	6413	0	0
T48	0	876	0	0
T67	0	132	0	0
T68	0	514	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	874117	0	0
T16	110232	7648	0	0
T17	0	7391	0	0
T23	108223	7581	0	0
T24	93090	0	0	0
T26	601627	3408	0	0
T31	176026	1160	0	0
T36	53095	0	0	0
T37	146825	0	0	0
T39	65387	0	0	0
T40	385799	259	0	0
T42	256621	6413	0	0
T48	0	876	0	0
T67	0	132	0	0
T68	0	514	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	874117	0	0
T16	110232	7648	0	0
T17	0	7391	0	0
T23	108223	7581	0	0
T24	93090	0	0	0
T26	601627	3408	0	0
T31	176026	1160	0	0
T36	53095	0	0	0
T37	146825	0	0	0
T39	65387	0	0	0
T40	385799	259	0	0
T42	256621	6413	0	0
T48	0	876	0	0
T67	0	132	0	0
T68	0	514	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	874117	0	0
T16	110232	7648	0	0
T17	0	7391	0	0
T23	108223	7581	0	0
T24	93090	0	0	0
T26	601627	3408	0	0
T31	176026	1160	0	0
T36	53095	0	0	0
T37	146825	0	0	0
T39	65387	0	0	0
T40	385799	259	0	0
T42	256621	6413	0	0
T48	0	876	0	0
T67	0	132	0	0
T68	0	514	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	123162524	0	0
T4	8302	8240	0	0
T5	87904	87904	0	0
T6	216	0	0	0
T7	34164	33734	0	0
T8	6658	6272	0	0
T9	80306	0	0	0
T10	11126	10910	0	0
T11	4427	4176	0	0
T12	10447	9920	0	0
T13	0	192256	0	0
T14	0	44912	0	0
T15	0	2800	0	0
T22	877	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152067546	874117	0	0
T16	110232	7648	0	0
T17	0	7391	0	0
T23	108223	7581	0	0
T24	93090	0	0	0
T26	601627	3408	0	0
T31	176026	1160	0	0
T36	53095	0	0	0
T37	146825	0	0	0
T39	65387	0	0	0
T40	385799	259	0	0
T42	256621	6413	0	0
T48	0	876	0	0
T67	0	132	0	0
T68	0	514	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T27,T29,T30

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T27,T29,T30
1	0	Covered	T4,T5,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T4,T5,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T29,T30
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T7
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	457290266	457198687	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	457290266	2251958	0	0
GntImpliesValid_A	457290266	2251958	0	0
GrantKnown_A	457290266	457198687	0	0
IdxKnown_A	457290266	457198687	0	0
IndexIsCorrect_A	457290266	2251958	0	0
LockArbDecision_A	457290266	0	0	0
NoReadyValidNoGrant_A	457290266	0	0	0
ReadyAndValidImplyGrant_A	457290266	2251958	0	0
ReqAndReadyImplyGrant_A	457290266	2251958	0	0
ReqImpliesValid_A	457290266	2251958	0	0
ReqStaysHighUntilGranted0_M	457290266	0	0	0
RoundRobin_A	457290266	3	0	976
ValidKnown_A	457290266	457198687	0	0
gen_data_port_assertion.DataFlow_A	457290266	2251958	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457290266	457198687	0	0
T1	332814	332748	0	0
T2	2184	2110	0	0
T3	7460	7362	0	0
T4	58997	58937	0	0
T5	618215	618157	0	0
T6	2614	2525	0	0
T7	280316	280238	0	0
T8	23892	23809	0	0
T9	51346	51283	0	0
T10	38390	38294	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457290266	2251958	0	0
T4	58997	832	0	0
T5	618215	832	0	0
T6	2614	0	0	0
T7	280316	832	0	0
T8	23892	832	0	0
T9	51346	0	0	0
T10	38390	832	0	0
T11	11591	832	0	0
T12	12007	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T22	2571	0	0	0
T27	0	45	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457290266	2251958	0	0
T4	58997	832	0	0
T5	618215	832	0	0
T6	2614	0	0	0
T7	280316	832	0	0
T8	23892	832	0	0
T9	51346	0	0	0
T10	38390	832	0	0
T11	11591	832	0	0
T12	12007	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T22	2571	0	0	0
T27	0	45	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457290266	457198687	0	0
T1	332814	332748	0	0
T2	2184	2110	0	0
T3	7460	7362	0	0
T4	58997	58937	0	0
T5	618215	618157	0	0
T6	2614	2525	0	0
T7	280316	280238	0	0
T8	23892	23809	0	0
T9	51346	51283	0	0
T10	38390	38294	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457290266	457198687	0	0
T1	332814	332748	0	0
T2	2184	2110	0	0
T3	7460	7362	0	0
T4	58997	58937	0	0
T5	618215	618157	0	0
T6	2614	2525	0	0
T7	280316	280238	0	0
T8	23892	23809	0	0
T9	51346	51283	0	0
T10	38390	38294	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457290266	2251958	0	0
T4	58997	832	0	0
T5	618215	832	0	0
T6	2614	0	0	0
T7	280316	832	0	0
T8	23892	832	0	0
T9	51346	0	0	0
T10	38390	832	0	0
T11	11591	832	0	0
T12	12007	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T22	2571	0	0	0
T27	0	45	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457290266	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457290266	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457290266	2251958	0	0
T4	58997	832	0	0
T5	618215	832	0	0
T6	2614	0	0	0
T7	280316	832	0	0
T8	23892	832	0	0
T9	51346	0	0	0
T10	38390	832	0	0
T11	11591	832	0	0
T12	12007	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T22	2571	0	0	0
T27	0	45	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457290266	2251958	0	0
T4	58997	832	0	0
T5	618215	832	0	0
T6	2614	0	0	0
T7	280316	832	0	0
T8	23892	832	0	0
T9	51346	0	0	0
T10	38390	832	0	0
T11	11591	832	0	0
T12	12007	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T22	2571	0	0	0
T27	0	45	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457290266	2251958	0	0
T4	58997	832	0	0
T5	618215	832	0	0
T6	2614	0	0	0
T7	280316	832	0	0
T8	23892	832	0	0
T9	51346	0	0	0
T10	38390	832	0	0
T11	11591	832	0	0
T12	12007	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T22	2571	0	0	0
T27	0	45	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	457290266	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457290266	3	0	976
T35	169534	0	0	1
T44	0	1	0	0
T57	213976	1	0	1
T58	0	1	0	0
T59	156810	0	0	1
T60	668908	0	0	1
T61	104419	0	0	1
T62	6861	0	0	1
T63	242538	0	0	1
T64	147311	0	0	1
T65	9584	0	0	1
T66	55661	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457290266	457198687	0	0
T1	332814	332748	0	0
T2	2184	2110	0	0
T3	7460	7362	0	0
T4	58997	58937	0	0
T5	618215	618157	0	0
T6	2614	2525	0	0
T7	280316	280238	0	0
T8	23892	23809	0	0
T9	51346	51283	0	0
T10	38390	38294	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457290266	2251958	0	0
T4	58997	832	0	0
T5	618215	832	0	0
T6	2614	0	0	0
T7	280316	832	0	0
T8	23892	832	0	0
T9	51346	0	0	0
T10	38390	832	0	0
T11	11591	832	0	0
T12	12007	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T22	2571	0	0	0
T27	0	45	0	0