Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
3547 |
0 |
0 |
T104 |
7510 |
88 |
0 |
0 |
T105 |
8225 |
5 |
0 |
0 |
T106 |
6519 |
96 |
0 |
0 |
T107 |
66366 |
1 |
0 |
0 |
T108 |
31378 |
1 |
0 |
0 |
T109 |
80510 |
5 |
0 |
0 |
T119 |
9563 |
3 |
0 |
0 |
T122 |
3759 |
13 |
0 |
0 |
T123 |
8062 |
2 |
0 |
0 |
T124 |
5450 |
1 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
2460 |
0 |
0 |
T107 |
66366 |
74 |
0 |
0 |
T108 |
31378 |
2 |
0 |
0 |
T119 |
9563 |
5 |
0 |
0 |
T120 |
5312 |
3 |
0 |
0 |
T124 |
5450 |
8 |
0 |
0 |
T127 |
81789 |
464 |
0 |
0 |
T129 |
77796 |
528 |
0 |
0 |
T134 |
69748 |
270 |
0 |
0 |
T162 |
13834 |
3 |
0 |
0 |
T163 |
17409 |
28 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
2571 |
0 |
0 |
T107 |
66366 |
67 |
0 |
0 |
T108 |
31378 |
31 |
0 |
0 |
T119 |
9563 |
9 |
0 |
0 |
T120 |
5312 |
16 |
0 |
0 |
T124 |
5450 |
3 |
0 |
0 |
T127 |
81789 |
575 |
0 |
0 |
T129 |
77796 |
443 |
0 |
0 |
T134 |
69748 |
300 |
0 |
0 |
T162 |
13834 |
15 |
0 |
0 |
T163 |
17409 |
35 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
3141 |
0 |
0 |
T107 |
66366 |
165 |
0 |
0 |
T108 |
31378 |
30 |
0 |
0 |
T119 |
9563 |
3 |
0 |
0 |
T120 |
5312 |
2 |
0 |
0 |
T124 |
5450 |
4 |
0 |
0 |
T127 |
81789 |
534 |
0 |
0 |
T129 |
77796 |
543 |
0 |
0 |
T134 |
69748 |
310 |
0 |
0 |
T162 |
13834 |
18 |
0 |
0 |
T163 |
17409 |
34 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
12023 |
0 |
0 |
T107 |
66366 |
1191 |
0 |
0 |
T108 |
31378 |
338 |
0 |
0 |
T119 |
9563 |
9 |
0 |
0 |
T120 |
5312 |
124 |
0 |
0 |
T124 |
5450 |
5 |
0 |
0 |
T127 |
81789 |
486 |
0 |
0 |
T129 |
77796 |
463 |
0 |
0 |
T134 |
69748 |
350 |
0 |
0 |
T162 |
13834 |
120 |
0 |
0 |
T163 |
17409 |
19 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
11604 |
0 |
0 |
T107 |
66366 |
1672 |
0 |
0 |
T108 |
31378 |
557 |
0 |
0 |
T119 |
9563 |
12 |
0 |
0 |
T120 |
5312 |
4 |
0 |
0 |
T124 |
5450 |
65 |
0 |
0 |
T127 |
81789 |
465 |
0 |
0 |
T129 |
77796 |
497 |
0 |
0 |
T134 |
69748 |
267 |
0 |
0 |
T162 |
13834 |
1 |
0 |
0 |
T163 |
17409 |
54 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
9947 |
0 |
0 |
T107 |
66366 |
1044 |
0 |
0 |
T108 |
31378 |
210 |
0 |
0 |
T113 |
24839 |
1 |
0 |
0 |
T119 |
9563 |
76 |
0 |
0 |
T120 |
5312 |
6 |
0 |
0 |
T124 |
5450 |
5 |
0 |
0 |
T127 |
81789 |
532 |
0 |
0 |
T129 |
77796 |
447 |
0 |
0 |
T162 |
13834 |
4 |
0 |
0 |
T163 |
17409 |
52 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
10440 |
0 |
0 |
T107 |
66366 |
1057 |
0 |
0 |
T108 |
31378 |
342 |
0 |
0 |
T119 |
9563 |
37 |
0 |
0 |
T120 |
5312 |
4 |
0 |
0 |
T124 |
5450 |
72 |
0 |
0 |
T127 |
81789 |
519 |
0 |
0 |
T129 |
77796 |
436 |
0 |
0 |
T134 |
69748 |
305 |
0 |
0 |
T162 |
13834 |
62 |
0 |
0 |
T163 |
17409 |
28 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
10023 |
0 |
0 |
T107 |
66366 |
768 |
0 |
0 |
T108 |
31378 |
341 |
0 |
0 |
T119 |
9563 |
86 |
0 |
0 |
T120 |
5312 |
145 |
0 |
0 |
T127 |
81789 |
471 |
0 |
0 |
T129 |
77796 |
509 |
0 |
0 |
T134 |
69748 |
264 |
0 |
0 |
T162 |
13834 |
133 |
0 |
0 |
T163 |
17409 |
51 |
0 |
0 |
T164 |
10493 |
105 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
10890 |
0 |
0 |
T107 |
66366 |
903 |
0 |
0 |
T108 |
31378 |
318 |
0 |
0 |
T119 |
9563 |
104 |
0 |
0 |
T120 |
5312 |
154 |
0 |
0 |
T124 |
5450 |
4 |
0 |
0 |
T127 |
81789 |
496 |
0 |
0 |
T129 |
77796 |
443 |
0 |
0 |
T134 |
69748 |
335 |
0 |
0 |
T162 |
13834 |
115 |
0 |
0 |
T163 |
17409 |
42 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
11448 |
0 |
0 |
T107 |
66366 |
1406 |
0 |
0 |
T108 |
31378 |
406 |
0 |
0 |
T119 |
9563 |
57 |
0 |
0 |
T120 |
5312 |
133 |
0 |
0 |
T124 |
5450 |
51 |
0 |
0 |
T127 |
81789 |
502 |
0 |
0 |
T129 |
77796 |
463 |
0 |
0 |
T134 |
69748 |
283 |
0 |
0 |
T162 |
13834 |
112 |
0 |
0 |
T163 |
17409 |
37 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
11445 |
0 |
0 |
T107 |
66366 |
1683 |
0 |
0 |
T108 |
31378 |
328 |
0 |
0 |
T119 |
9563 |
58 |
0 |
0 |
T120 |
5312 |
9 |
0 |
0 |
T124 |
5450 |
77 |
0 |
0 |
T127 |
81789 |
504 |
0 |
0 |
T129 |
77796 |
516 |
0 |
0 |
T134 |
69748 |
286 |
0 |
0 |
T162 |
13834 |
74 |
0 |
0 |
T163 |
17409 |
38 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
6078 |
0 |
0 |
T107 |
66366 |
471 |
0 |
0 |
T108 |
31378 |
146 |
0 |
0 |
T119 |
9563 |
19 |
0 |
0 |
T120 |
5312 |
53 |
0 |
0 |
T124 |
5450 |
2 |
0 |
0 |
T127 |
81789 |
547 |
0 |
0 |
T129 |
77796 |
466 |
0 |
0 |
T134 |
69748 |
323 |
0 |
0 |
T162 |
13834 |
81 |
0 |
0 |
T163 |
17409 |
59 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
6251 |
0 |
0 |
T107 |
66366 |
695 |
0 |
0 |
T108 |
31378 |
156 |
0 |
0 |
T113 |
24839 |
4 |
0 |
0 |
T119 |
9563 |
47 |
0 |
0 |
T120 |
5312 |
63 |
0 |
0 |
T124 |
5450 |
5 |
0 |
0 |
T127 |
81789 |
487 |
0 |
0 |
T129 |
77796 |
507 |
0 |
0 |
T162 |
13834 |
16 |
0 |
0 |
T163 |
17409 |
54 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
6315 |
0 |
0 |
T107 |
66366 |
606 |
0 |
0 |
T108 |
31378 |
108 |
0 |
0 |
T119 |
9563 |
41 |
0 |
0 |
T120 |
5312 |
75 |
0 |
0 |
T124 |
5450 |
12 |
0 |
0 |
T127 |
81789 |
544 |
0 |
0 |
T129 |
77796 |
523 |
0 |
0 |
T134 |
69748 |
269 |
0 |
0 |
T162 |
13834 |
58 |
0 |
0 |
T163 |
17409 |
23 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
6326 |
0 |
0 |
T107 |
66366 |
622 |
0 |
0 |
T108 |
31378 |
170 |
0 |
0 |
T119 |
9563 |
54 |
0 |
0 |
T120 |
5312 |
4 |
0 |
0 |
T127 |
81789 |
555 |
0 |
0 |
T129 |
77796 |
504 |
0 |
0 |
T134 |
69748 |
358 |
0 |
0 |
T162 |
13834 |
64 |
0 |
0 |
T163 |
17409 |
50 |
0 |
0 |
T164 |
10493 |
65 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
5995 |
0 |
0 |
T107 |
66366 |
586 |
0 |
0 |
T108 |
31378 |
132 |
0 |
0 |
T119 |
9563 |
34 |
0 |
0 |
T120 |
5312 |
74 |
0 |
0 |
T124 |
5450 |
4 |
0 |
0 |
T127 |
81789 |
474 |
0 |
0 |
T129 |
77796 |
461 |
0 |
0 |
T134 |
69748 |
296 |
0 |
0 |
T162 |
13834 |
88 |
0 |
0 |
T163 |
17409 |
24 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
6042 |
0 |
0 |
T107 |
66366 |
773 |
0 |
0 |
T108 |
31378 |
170 |
0 |
0 |
T119 |
9563 |
14 |
0 |
0 |
T120 |
5312 |
10 |
0 |
0 |
T124 |
5450 |
36 |
0 |
0 |
T127 |
81789 |
462 |
0 |
0 |
T129 |
77796 |
474 |
0 |
0 |
T134 |
69748 |
325 |
0 |
0 |
T162 |
13834 |
52 |
0 |
0 |
T163 |
17409 |
44 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
5530 |
0 |
0 |
T107 |
66366 |
393 |
0 |
0 |
T108 |
31378 |
112 |
0 |
0 |
T119 |
9563 |
7 |
0 |
0 |
T120 |
5312 |
48 |
0 |
0 |
T124 |
5450 |
3 |
0 |
0 |
T127 |
81789 |
445 |
0 |
0 |
T129 |
77796 |
464 |
0 |
0 |
T134 |
69748 |
316 |
0 |
0 |
T162 |
13834 |
10 |
0 |
0 |
T163 |
17409 |
49 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
6044 |
0 |
0 |
T107 |
66366 |
775 |
0 |
0 |
T108 |
31378 |
131 |
0 |
0 |
T119 |
9563 |
37 |
0 |
0 |
T120 |
5312 |
3 |
0 |
0 |
T124 |
5450 |
19 |
0 |
0 |
T127 |
81789 |
528 |
0 |
0 |
T129 |
77796 |
452 |
0 |
0 |
T134 |
69748 |
304 |
0 |
0 |
T162 |
13834 |
51 |
0 |
0 |
T163 |
17409 |
20 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
6038 |
0 |
0 |
T107 |
66366 |
539 |
0 |
0 |
T108 |
31378 |
166 |
0 |
0 |
T119 |
9563 |
11 |
0 |
0 |
T120 |
5312 |
4 |
0 |
0 |
T124 |
5450 |
5 |
0 |
0 |
T127 |
81789 |
496 |
0 |
0 |
T129 |
77796 |
473 |
0 |
0 |
T134 |
69748 |
315 |
0 |
0 |
T162 |
13834 |
74 |
0 |
0 |
T163 |
17409 |
17 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
5846 |
0 |
0 |
T107 |
66366 |
443 |
0 |
0 |
T108 |
31378 |
86 |
0 |
0 |
T119 |
9563 |
30 |
0 |
0 |
T120 |
5312 |
38 |
0 |
0 |
T124 |
5450 |
1 |
0 |
0 |
T127 |
81789 |
529 |
0 |
0 |
T129 |
77796 |
529 |
0 |
0 |
T134 |
69748 |
236 |
0 |
0 |
T162 |
13834 |
106 |
0 |
0 |
T163 |
17409 |
8 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
6285 |
0 |
0 |
T106 |
6519 |
10 |
0 |
0 |
T107 |
66366 |
601 |
0 |
0 |
T108 |
31378 |
106 |
0 |
0 |
T119 |
9563 |
56 |
0 |
0 |
T120 |
5312 |
57 |
0 |
0 |
T124 |
5450 |
6 |
0 |
0 |
T127 |
81789 |
582 |
0 |
0 |
T129 |
77796 |
440 |
0 |
0 |
T162 |
13834 |
18 |
0 |
0 |
T163 |
17409 |
31 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
6017 |
0 |
0 |
T107 |
66366 |
683 |
0 |
0 |
T108 |
31378 |
171 |
0 |
0 |
T119 |
9563 |
40 |
0 |
0 |
T120 |
5312 |
9 |
0 |
0 |
T124 |
5450 |
25 |
0 |
0 |
T127 |
81789 |
483 |
0 |
0 |
T129 |
77796 |
466 |
0 |
0 |
T134 |
69748 |
282 |
0 |
0 |
T162 |
13834 |
38 |
0 |
0 |
T163 |
17409 |
44 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
6030 |
0 |
0 |
T107 |
66366 |
359 |
0 |
0 |
T108 |
31378 |
102 |
0 |
0 |
T119 |
9563 |
37 |
0 |
0 |
T120 |
5312 |
6 |
0 |
0 |
T124 |
5450 |
24 |
0 |
0 |
T127 |
81789 |
485 |
0 |
0 |
T129 |
77796 |
480 |
0 |
0 |
T134 |
69748 |
322 |
0 |
0 |
T162 |
13834 |
58 |
0 |
0 |
T163 |
17409 |
22 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
6136 |
0 |
0 |
T107 |
66366 |
564 |
0 |
0 |
T108 |
31378 |
94 |
0 |
0 |
T119 |
9563 |
34 |
0 |
0 |
T120 |
5312 |
8 |
0 |
0 |
T124 |
5450 |
6 |
0 |
0 |
T127 |
81789 |
448 |
0 |
0 |
T129 |
77796 |
486 |
0 |
0 |
T134 |
69748 |
305 |
0 |
0 |
T162 |
13834 |
59 |
0 |
0 |
T163 |
17409 |
37 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
5621 |
0 |
0 |
T107 |
66366 |
545 |
0 |
0 |
T108 |
31378 |
79 |
0 |
0 |
T120 |
5312 |
11 |
0 |
0 |
T124 |
5450 |
14 |
0 |
0 |
T127 |
81789 |
508 |
0 |
0 |
T129 |
77796 |
528 |
0 |
0 |
T134 |
69748 |
308 |
0 |
0 |
T162 |
13834 |
62 |
0 |
0 |
T163 |
17409 |
50 |
0 |
0 |
T164 |
10493 |
13 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
6102 |
0 |
0 |
T107 |
66366 |
552 |
0 |
0 |
T108 |
31378 |
129 |
0 |
0 |
T113 |
24839 |
9 |
0 |
0 |
T119 |
9563 |
56 |
0 |
0 |
T120 |
5312 |
64 |
0 |
0 |
T124 |
5450 |
1 |
0 |
0 |
T127 |
81789 |
502 |
0 |
0 |
T129 |
77796 |
471 |
0 |
0 |
T162 |
13834 |
24 |
0 |
0 |
T163 |
17409 |
63 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
5745 |
0 |
0 |
T107 |
66366 |
480 |
0 |
0 |
T108 |
31378 |
183 |
0 |
0 |
T119 |
9563 |
26 |
0 |
0 |
T120 |
5312 |
4 |
0 |
0 |
T124 |
5450 |
5 |
0 |
0 |
T127 |
81789 |
498 |
0 |
0 |
T129 |
77796 |
471 |
0 |
0 |
T134 |
69748 |
325 |
0 |
0 |
T162 |
13834 |
107 |
0 |
0 |
T163 |
17409 |
35 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
6132 |
0 |
0 |
T107 |
66366 |
497 |
0 |
0 |
T108 |
31378 |
207 |
0 |
0 |
T113 |
24839 |
2 |
0 |
0 |
T119 |
9563 |
65 |
0 |
0 |
T120 |
5312 |
10 |
0 |
0 |
T124 |
5450 |
9 |
0 |
0 |
T127 |
81789 |
552 |
0 |
0 |
T129 |
77796 |
496 |
0 |
0 |
T162 |
13834 |
21 |
0 |
0 |
T163 |
17409 |
23 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
5419 |
0 |
0 |
T104 |
7510 |
8 |
0 |
0 |
T107 |
66366 |
446 |
0 |
0 |
T108 |
31378 |
135 |
0 |
0 |
T119 |
9563 |
36 |
0 |
0 |
T120 |
5312 |
7 |
0 |
0 |
T124 |
5450 |
36 |
0 |
0 |
T127 |
81789 |
491 |
0 |
0 |
T129 |
77796 |
543 |
0 |
0 |
T162 |
13834 |
35 |
0 |
0 |
T163 |
17409 |
31 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
6093 |
0 |
0 |
T107 |
66366 |
410 |
0 |
0 |
T108 |
31378 |
166 |
0 |
0 |
T119 |
9563 |
53 |
0 |
0 |
T120 |
5312 |
3 |
0 |
0 |
T124 |
5450 |
11 |
0 |
0 |
T127 |
81789 |
565 |
0 |
0 |
T129 |
77796 |
447 |
0 |
0 |
T134 |
69748 |
311 |
0 |
0 |
T162 |
13834 |
45 |
0 |
0 |
T163 |
17409 |
29 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
6189 |
0 |
0 |
T107 |
66366 |
708 |
0 |
0 |
T108 |
31378 |
147 |
0 |
0 |
T113 |
24839 |
1 |
0 |
0 |
T119 |
9563 |
23 |
0 |
0 |
T120 |
5312 |
3 |
0 |
0 |
T124 |
5450 |
8 |
0 |
0 |
T127 |
81789 |
478 |
0 |
0 |
T129 |
77796 |
443 |
0 |
0 |
T162 |
13834 |
44 |
0 |
0 |
T163 |
17409 |
34 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
6095 |
0 |
0 |
T107 |
66366 |
650 |
0 |
0 |
T108 |
31378 |
131 |
0 |
0 |
T119 |
9563 |
29 |
0 |
0 |
T120 |
5312 |
33 |
0 |
0 |
T124 |
5450 |
29 |
0 |
0 |
T127 |
81789 |
505 |
0 |
0 |
T129 |
77796 |
558 |
0 |
0 |
T134 |
69748 |
269 |
0 |
0 |
T162 |
13834 |
42 |
0 |
0 |
T163 |
17409 |
15 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
5869 |
0 |
0 |
T107 |
66366 |
480 |
0 |
0 |
T108 |
31378 |
138 |
0 |
0 |
T119 |
9563 |
37 |
0 |
0 |
T120 |
5312 |
68 |
0 |
0 |
T124 |
5450 |
59 |
0 |
0 |
T127 |
81789 |
480 |
0 |
0 |
T129 |
77796 |
472 |
0 |
0 |
T134 |
69748 |
293 |
0 |
0 |
T162 |
13834 |
15 |
0 |
0 |
T163 |
17409 |
19 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
6210 |
0 |
0 |
T107 |
66366 |
432 |
0 |
0 |
T108 |
31378 |
121 |
0 |
0 |
T119 |
9563 |
14 |
0 |
0 |
T120 |
5312 |
54 |
0 |
0 |
T124 |
5450 |
37 |
0 |
0 |
T127 |
81789 |
495 |
0 |
0 |
T129 |
77796 |
523 |
0 |
0 |
T134 |
69748 |
256 |
0 |
0 |
T162 |
13834 |
68 |
0 |
0 |
T163 |
17409 |
7 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
3000 |
0 |
0 |
T107 |
66366 |
131 |
0 |
0 |
T108 |
31378 |
45 |
0 |
0 |
T113 |
24839 |
2 |
0 |
0 |
T119 |
9563 |
7 |
0 |
0 |
T120 |
5312 |
16 |
0 |
0 |
T124 |
5450 |
9 |
0 |
0 |
T127 |
81789 |
523 |
0 |
0 |
T129 |
77796 |
449 |
0 |
0 |
T162 |
13834 |
29 |
0 |
0 |
T163 |
17409 |
36 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
3018 |
0 |
0 |
T107 |
66366 |
167 |
0 |
0 |
T108 |
31378 |
25 |
0 |
0 |
T119 |
9563 |
13 |
0 |
0 |
T120 |
5312 |
10 |
0 |
0 |
T124 |
5450 |
8 |
0 |
0 |
T127 |
81789 |
527 |
0 |
0 |
T129 |
77796 |
480 |
0 |
0 |
T134 |
69748 |
329 |
0 |
0 |
T162 |
13834 |
14 |
0 |
0 |
T163 |
17409 |
52 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
2949 |
0 |
0 |
T107 |
66366 |
128 |
0 |
0 |
T108 |
31378 |
35 |
0 |
0 |
T113 |
24839 |
4 |
0 |
0 |
T119 |
9563 |
7 |
0 |
0 |
T120 |
5312 |
3 |
0 |
0 |
T124 |
5450 |
4 |
0 |
0 |
T127 |
81789 |
519 |
0 |
0 |
T129 |
77796 |
513 |
0 |
0 |
T162 |
13834 |
19 |
0 |
0 |
T163 |
17409 |
24 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
2858 |
0 |
0 |
T107 |
66366 |
130 |
0 |
0 |
T108 |
31378 |
26 |
0 |
0 |
T119 |
9563 |
11 |
0 |
0 |
T120 |
5312 |
10 |
0 |
0 |
T124 |
5450 |
6 |
0 |
0 |
T127 |
81789 |
537 |
0 |
0 |
T129 |
77796 |
495 |
0 |
0 |
T134 |
69748 |
296 |
0 |
0 |
T162 |
13834 |
8 |
0 |
0 |
T163 |
17409 |
28 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
3486 |
0 |
0 |
T107 |
66366 |
219 |
0 |
0 |
T108 |
31378 |
75 |
0 |
0 |
T119 |
9563 |
14 |
0 |
0 |
T120 |
5312 |
3 |
0 |
0 |
T124 |
5450 |
9 |
0 |
0 |
T127 |
81789 |
505 |
0 |
0 |
T129 |
77796 |
539 |
0 |
0 |
T134 |
69748 |
337 |
0 |
0 |
T162 |
13834 |
32 |
0 |
0 |
T163 |
17409 |
29 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
5770 |
0 |
0 |
T19 |
7846 |
94 |
0 |
0 |
T21 |
0 |
43 |
0 |
0 |
T34 |
0 |
21 |
0 |
0 |
T89 |
0 |
35 |
0 |
0 |
T165 |
0 |
65 |
0 |
0 |
T166 |
0 |
19 |
0 |
0 |
T167 |
0 |
35 |
0 |
0 |
T168 |
0 |
38 |
0 |
0 |
T169 |
0 |
26 |
0 |
0 |
T170 |
0 |
24 |
0 |
0 |
T171 |
1131 |
0 |
0 |
0 |
T172 |
1663 |
0 |
0 |
0 |
T173 |
11832 |
0 |
0 |
0 |
T174 |
2037 |
0 |
0 |
0 |
T175 |
281844 |
0 |
0 |
0 |
T176 |
1646 |
0 |
0 |
0 |
T177 |
105837 |
0 |
0 |
0 |
T178 |
12046 |
0 |
0 |
0 |
T179 |
154192 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
2796 |
0 |
0 |
T107 |
66366 |
108 |
0 |
0 |
T108 |
31378 |
25 |
0 |
0 |
T119 |
9563 |
7 |
0 |
0 |
T120 |
5312 |
9 |
0 |
0 |
T127 |
81789 |
494 |
0 |
0 |
T129 |
77796 |
487 |
0 |
0 |
T134 |
69748 |
260 |
0 |
0 |
T162 |
13834 |
31 |
0 |
0 |
T163 |
17409 |
63 |
0 |
0 |
T164 |
10493 |
19 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
2904 |
0 |
0 |
T107 |
66366 |
136 |
0 |
0 |
T108 |
31378 |
27 |
0 |
0 |
T119 |
9563 |
8 |
0 |
0 |
T120 |
5312 |
8 |
0 |
0 |
T124 |
5450 |
3 |
0 |
0 |
T127 |
81789 |
465 |
0 |
0 |
T129 |
77796 |
492 |
0 |
0 |
T134 |
69748 |
314 |
0 |
0 |
T162 |
13834 |
5 |
0 |
0 |
T163 |
17409 |
31 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
2621 |
0 |
0 |
T107 |
66366 |
64 |
0 |
0 |
T108 |
31378 |
16 |
0 |
0 |
T119 |
9563 |
6 |
0 |
0 |
T120 |
5312 |
9 |
0 |
0 |
T124 |
5450 |
5 |
0 |
0 |
T127 |
81789 |
502 |
0 |
0 |
T129 |
77796 |
444 |
0 |
0 |
T134 |
69748 |
326 |
0 |
0 |
T162 |
13834 |
33 |
0 |
0 |
T163 |
17409 |
46 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
2588 |
0 |
0 |
T107 |
66366 |
79 |
0 |
0 |
T108 |
31378 |
18 |
0 |
0 |
T119 |
9563 |
7 |
0 |
0 |
T120 |
5312 |
9 |
0 |
0 |
T124 |
5450 |
7 |
0 |
0 |
T127 |
81789 |
485 |
0 |
0 |
T129 |
77796 |
509 |
0 |
0 |
T134 |
69748 |
267 |
0 |
0 |
T162 |
13834 |
14 |
0 |
0 |
T163 |
17409 |
19 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
2465 |
0 |
0 |
T107 |
66366 |
83 |
0 |
0 |
T108 |
31378 |
21 |
0 |
0 |
T119 |
9563 |
4 |
0 |
0 |
T120 |
5312 |
9 |
0 |
0 |
T124 |
5450 |
3 |
0 |
0 |
T127 |
81789 |
510 |
0 |
0 |
T129 |
77796 |
436 |
0 |
0 |
T134 |
69748 |
272 |
0 |
0 |
T162 |
13834 |
13 |
0 |
0 |
T163 |
17409 |
41 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
2643 |
0 |
0 |
T107 |
66366 |
63 |
0 |
0 |
T108 |
31378 |
22 |
0 |
0 |
T119 |
9563 |
8 |
0 |
0 |
T120 |
5312 |
6 |
0 |
0 |
T124 |
5450 |
2 |
0 |
0 |
T127 |
81789 |
591 |
0 |
0 |
T129 |
77796 |
500 |
0 |
0 |
T134 |
69748 |
253 |
0 |
0 |
T162 |
13834 |
7 |
0 |
0 |
T163 |
17409 |
33 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
3380 |
0 |
0 |
T107 |
66366 |
134 |
0 |
0 |
T108 |
31378 |
60 |
0 |
0 |
T119 |
9563 |
17 |
0 |
0 |
T120 |
5312 |
8 |
0 |
0 |
T124 |
5450 |
19 |
0 |
0 |
T127 |
81789 |
462 |
0 |
0 |
T129 |
77796 |
503 |
0 |
0 |
T134 |
69748 |
295 |
0 |
0 |
T162 |
13834 |
34 |
0 |
0 |
T163 |
17409 |
61 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
2433 |
0 |
0 |
T107 |
66366 |
88 |
0 |
0 |
T108 |
31378 |
29 |
0 |
0 |
T119 |
9563 |
5 |
0 |
0 |
T120 |
5312 |
8 |
0 |
0 |
T127 |
81789 |
524 |
0 |
0 |
T129 |
77796 |
448 |
0 |
0 |
T134 |
69748 |
222 |
0 |
0 |
T162 |
13834 |
10 |
0 |
0 |
T163 |
17409 |
22 |
0 |
0 |
T164 |
10493 |
10 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
3741 |
0 |
0 |
T107 |
66366 |
264 |
0 |
0 |
T108 |
31378 |
87 |
0 |
0 |
T113 |
24839 |
7 |
0 |
0 |
T119 |
9563 |
10 |
0 |
0 |
T120 |
5312 |
9 |
0 |
0 |
T124 |
5450 |
8 |
0 |
0 |
T127 |
81789 |
494 |
0 |
0 |
T129 |
77796 |
421 |
0 |
0 |
T162 |
13834 |
27 |
0 |
0 |
T163 |
17409 |
30 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
2726 |
0 |
0 |
T107 |
66366 |
116 |
0 |
0 |
T108 |
31378 |
21 |
0 |
0 |
T119 |
9563 |
12 |
0 |
0 |
T120 |
5312 |
5 |
0 |
0 |
T127 |
81789 |
507 |
0 |
0 |
T129 |
77796 |
455 |
0 |
0 |
T134 |
69748 |
224 |
0 |
0 |
T162 |
13834 |
19 |
0 |
0 |
T163 |
17409 |
34 |
0 |
0 |
T164 |
10493 |
25 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
2687 |
0 |
0 |
T107 |
66366 |
101 |
0 |
0 |
T108 |
31378 |
15 |
0 |
0 |
T119 |
9563 |
14 |
0 |
0 |
T120 |
5312 |
6 |
0 |
0 |
T124 |
5450 |
3 |
0 |
0 |
T127 |
81789 |
494 |
0 |
0 |
T129 |
77796 |
540 |
0 |
0 |
T134 |
69748 |
309 |
0 |
0 |
T162 |
13834 |
11 |
0 |
0 |
T163 |
17409 |
10 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
2552 |
0 |
0 |
T104 |
7510 |
8 |
0 |
0 |
T107 |
66366 |
80 |
0 |
0 |
T108 |
31378 |
40 |
0 |
0 |
T119 |
9563 |
12 |
0 |
0 |
T120 |
5312 |
9 |
0 |
0 |
T124 |
5450 |
4 |
0 |
0 |
T127 |
81789 |
476 |
0 |
0 |
T129 |
77796 |
419 |
0 |
0 |
T162 |
13834 |
4 |
0 |
0 |
T163 |
17409 |
31 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
2615 |
0 |
0 |
T107 |
66366 |
73 |
0 |
0 |
T108 |
31378 |
18 |
0 |
0 |
T119 |
9563 |
11 |
0 |
0 |
T120 |
5312 |
2 |
0 |
0 |
T124 |
5450 |
10 |
0 |
0 |
T127 |
81789 |
515 |
0 |
0 |
T129 |
77796 |
462 |
0 |
0 |
T134 |
69748 |
324 |
0 |
0 |
T162 |
13834 |
10 |
0 |
0 |
T163 |
17409 |
54 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
2613 |
0 |
0 |
T107 |
66366 |
66 |
0 |
0 |
T108 |
31378 |
17 |
0 |
0 |
T119 |
9563 |
15 |
0 |
0 |
T120 |
5312 |
7 |
0 |
0 |
T127 |
81789 |
544 |
0 |
0 |
T129 |
77796 |
465 |
0 |
0 |
T134 |
69748 |
318 |
0 |
0 |
T162 |
13834 |
10 |
0 |
0 |
T163 |
17409 |
17 |
0 |
0 |
T164 |
10493 |
24 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
2631 |
0 |
0 |
T104 |
7510 |
4 |
0 |
0 |
T107 |
66366 |
91 |
0 |
0 |
T108 |
31378 |
25 |
0 |
0 |
T119 |
9563 |
3 |
0 |
0 |
T120 |
5312 |
8 |
0 |
0 |
T124 |
5450 |
6 |
0 |
0 |
T127 |
81789 |
559 |
0 |
0 |
T129 |
77796 |
481 |
0 |
0 |
T162 |
13834 |
13 |
0 |
0 |
T163 |
17409 |
41 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459473188 |
2521 |
0 |
0 |
T107 |
66366 |
76 |
0 |
0 |
T108 |
31378 |
19 |
0 |
0 |
T119 |
9563 |
6 |
0 |
0 |
T120 |
5312 |
6 |
0 |
0 |
T127 |
81789 |
553 |
0 |
0 |
T129 |
77796 |
442 |
0 |
0 |
T134 |
69748 |
249 |
0 |
0 |
T162 |
13834 |
17 |
0 |
0 |
T163 |
17409 |
23 |
0 |
0 |
T164 |
10493 |
20 |
0 |
0 |