Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3929017	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4437521

1

T1

1619

T2

1

T3

3558

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4622437	1			T1	5011		T2	1		T3	5276
values[0x0]	1872054	1			T1	809		T2	1		T3	419
values[0x1]	1872047	1			T1	817		T3	464		T4	437

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2772894	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5593644

1

T1

3289

T2

1

T3

4059

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	32291	1			T3	26		T4	3		T6	118
valid_sources[0x01]	31779	1			T3	11		T4	5		T6	176
valid_sources[0x02]	31083	1			T1	489		T3	25		T4	5
valid_sources[0x03]	30519	1			T3	33		T4	1		T6	185
valid_sources[0x04]	29878	1			T3	30		T4	4		T6	169
valid_sources[0x05]	29667	1			T3	23		T4	3		T6	147
valid_sources[0x06]	34910	1			T3	38		T4	8		T6	130
valid_sources[0x07]	31054	1			T3	12		T4	3		T6	131
valid_sources[0x08]	30084	1			T3	20		T4	6		T6	160
valid_sources[0x09]	28394	1			T3	21		T4	5		T6	151
valid_sources[0x0a]	29476	1			T3	3		T4	3		T6	153
valid_sources[0x0b]	31704	1			T3	23		T4	3		T6	156
valid_sources[0x0c]	32309	1			T3	6		T4	6		T6	213
valid_sources[0x0d]	31334	1			T3	39		T4	1		T6	162
valid_sources[0x0e]	33984	1			T3	17		T4	5		T6	116
valid_sources[0x0f]	29343	1			T3	8		T4	4		T6	151
valid_sources[0x10]	31576	1			T3	7		T4	5		T6	140
valid_sources[0x11]	29824	1			T3	24		T4	1		T6	128
valid_sources[0x12]	33756	1			T3	24		T4	2		T6	159
valid_sources[0x13]	30903	1			T3	25		T4	6		T6	139
valid_sources[0x14]	29096	1			T1	1		T3	22		T4	4
valid_sources[0x15]	32572	1			T3	9		T4	4		T6	158
valid_sources[0x16]	31141	1			T3	22		T4	5		T6	170
valid_sources[0x17]	31042	1			T1	1		T3	34		T4	2
valid_sources[0x18]	30355	1			T3	12		T4	7		T6	152
valid_sources[0x19]	32840	1			T3	4		T4	5		T6	167
valid_sources[0x1a]	30967	1			T3	9		T4	1		T6	166
valid_sources[0x1b]	31675	1			T3	22		T4	3		T6	162
valid_sources[0x1c]	31993	1			T3	42		T4	5		T6	146
valid_sources[0x1d]	31013	1			T3	21		T4	3		T6	157
valid_sources[0x1e]	29822	1			T3	37		T4	2		T6	157
valid_sources[0x1f]	33756	1			T3	14		T4	2		T6	173
valid_sources[0x20]	30587	1			T3	16		T4	4		T6	146
valid_sources[0x21]	29914	1			T3	22		T4	7		T6	183
valid_sources[0x22]	30477	1			T3	39		T4	1		T6	165
valid_sources[0x23]	34828	1			T3	31		T4	7		T6	171
valid_sources[0x24]	32094	1			T3	33		T4	5		T6	157
valid_sources[0x25]	29714	1			T3	24		T4	5		T6	143
valid_sources[0x26]	32475	1			T3	22		T4	6		T6	151
valid_sources[0x27]	32404	1			T3	34		T4	6		T6	156
valid_sources[0x28]	34012	1			T3	24		T4	3		T6	161
valid_sources[0x29]	29130	1			T3	39		T4	4		T6	129
valid_sources[0x2a]	32871	1			T3	29		T4	2		T6	146
valid_sources[0x2b]	32782	1			T3	40		T4	8		T6	131
valid_sources[0x2c]	32050	1			T1	1		T3	25		T4	4
valid_sources[0x2d]	31902	1			T3	18		T4	5		T6	167
valid_sources[0x2e]	33454	1			T1	1		T3	25		T4	2
valid_sources[0x2f]	34007	1			T3	15		T4	5		T6	161
valid_sources[0x30]	33513	1			T3	13		T4	2		T6	139
valid_sources[0x31]	30968	1			T3	21		T4	2		T6	166
valid_sources[0x32]	31432	1			T3	5		T4	3		T6	171
valid_sources[0x33]	35912	1			T1	1		T3	32		T4	7
valid_sources[0x34]	30401	1			T3	26		T4	4		T6	168
valid_sources[0x35]	34169	1			T1	258		T3	41		T4	6
valid_sources[0x36]	31525	1			T3	24		T4	7		T6	171
valid_sources[0x37]	33978	1			T3	16		T4	3		T6	134
valid_sources[0x38]	35283	1			T3	24		T4	4		T6	152
valid_sources[0x39]	34887	1			T3	12		T6	170		T7	5
valid_sources[0x3a]	32930	1			T3	37		T4	1		T6	166
valid_sources[0x3b]	33977	1			T1	1		T3	33		T4	4
valid_sources[0x3c]	38780	1			T3	40		T4	2		T6	155
valid_sources[0x3d]	33573	1			T1	1		T3	50		T4	4
valid_sources[0x3e]	43884	1			T3	4		T4	3		T6	149
valid_sources[0x3f]	29668	1			T3	9		T4	2		T6	150
valid_sources[0x40]	30701	1			T3	46		T4	3		T6	163
valid_sources[0x41]	28314	1			T3	69		T4	6		T6	168
valid_sources[0x42]	34621	1			T3	17		T6	142		T7	4
valid_sources[0x43]	35085	1			T3	35		T4	5		T6	154
valid_sources[0x44]	30358	1			T3	27		T4	4		T6	140
valid_sources[0x45]	35880	1			T3	27		T4	1		T6	173
valid_sources[0x46]	31199	1			T3	23		T4	1		T6	169
valid_sources[0x47]	34596	1			T3	35		T4	5		T6	118
valid_sources[0x48]	34595	1			T1	1		T3	21		T4	3
valid_sources[0x49]	31014	1			T3	26		T4	7		T6	133
valid_sources[0x4a]	31556	1			T3	27		T4	3		T6	161
valid_sources[0x4b]	30678	1			T3	53		T4	3		T6	155
valid_sources[0x4c]	30392	1			T1	78		T3	31		T4	5
valid_sources[0x4d]	31273	1			T3	17		T4	3		T6	155
valid_sources[0x4e]	32054	1			T3	11		T4	1		T6	173
valid_sources[0x4f]	32649	1			T3	17		T4	2		T6	148
valid_sources[0x50]	36825	1			T3	7		T4	6		T6	152
valid_sources[0x51]	33691	1			T3	22		T4	5		T6	152
valid_sources[0x52]	35013	1			T3	25		T4	5		T6	128
valid_sources[0x53]	31798	1			T3	44		T4	3		T6	176
valid_sources[0x54]	32786	1			T3	20		T4	4		T6	173
valid_sources[0x55]	33717	1			T3	27		T4	7		T6	134
valid_sources[0x56]	31432	1			T3	38		T4	7		T6	171
valid_sources[0x57]	35469	1			T3	18		T4	4		T6	172
valid_sources[0x58]	35393	1			T3	28		T4	4		T6	168
valid_sources[0x59]	34810	1			T3	25		T4	4		T6	187
valid_sources[0x5a]	30905	1			T3	11		T4	2		T6	131
valid_sources[0x5b]	32888	1			T3	27		T4	3		T6	138
valid_sources[0x5c]	33140	1			T3	17		T4	1		T6	151
valid_sources[0x5d]	29517	1			T3	8		T4	5		T6	137
valid_sources[0x5e]	28768	1			T3	3		T4	4		T6	155
valid_sources[0x5f]	32276	1			T1	270		T3	16		T4	5
valid_sources[0x60]	33661	1			T3	48		T4	2		T6	127
valid_sources[0x61]	33030	1			T3	42		T4	1		T6	193
valid_sources[0x62]	46073	1			T3	44		T4	8		T6	166
valid_sources[0x63]	33963	1			T3	5		T4	4		T6	148
valid_sources[0x64]	31419	1			T3	35		T4	3		T6	160
valid_sources[0x65]	33274	1			T3	11		T4	4		T6	184
valid_sources[0x66]	32782	1			T3	24		T4	4		T6	151
valid_sources[0x67]	30274	1			T3	28		T4	2		T6	148
valid_sources[0x68]	34248	1			T3	20		T4	3		T6	183
valid_sources[0x69]	35883	1			T3	16		T4	3		T6	172
valid_sources[0x6a]	31554	1			T3	36		T4	5		T6	153
valid_sources[0x6b]	30768	1			T3	29		T4	4		T6	161
valid_sources[0x6c]	30511	1			T3	28		T4	2		T6	163
valid_sources[0x6d]	29785	1			T1	1753		T3	34		T4	2
valid_sources[0x6e]	31416	1			T3	24		T4	1		T6	159
valid_sources[0x6f]	30491	1			T3	9		T4	1		T6	152
valid_sources[0x70]	35276	1			T3	43		T4	6		T6	155
valid_sources[0x71]	32822	1			T3	23		T4	3		T6	124
valid_sources[0x72]	35499	1			T3	29		T4	1		T6	134
valid_sources[0x73]	33721	1			T3	15		T4	2		T6	163
valid_sources[0x74]	32047	1			T3	13		T4	6		T6	164
valid_sources[0x75]	29935	1			T3	39		T4	2		T6	165
valid_sources[0x76]	31993	1			T3	30		T4	4		T6	146
valid_sources[0x77]	31123	1			T3	33		T4	8		T6	135
valid_sources[0x78]	84175	1			T3	31		T4	1		T6	148
valid_sources[0x79]	33169	1			T3	22		T4	8		T6	153
valid_sources[0x7a]	33769	1			T3	31		T4	3		T6	151
valid_sources[0x7b]	34834	1			T3	33		T4	2		T6	147
valid_sources[0x7c]	32563	1			T3	53		T4	4		T6	162
valid_sources[0x7d]	33981	1			T3	44		T6	135		T8	328
valid_sources[0x7e]	36020	1			T1	1		T3	13		T4	8
valid_sources[0x7f]	29835	1			T3	27		T4	2		T6	134
valid_sources[0x80]	33769	1			T3	11		T4	6		T6	140

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1046031

1

T1

367

T3

2681

T4

53

values[0x0]

all_enables

biggest_size

1707394

1

T1

640

T2

1

T3

419

values[0x1]

all_enables

biggest_size

1684096

1

T1

612

T3

458

T4

430