Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3950501

1

T1

5018

T2

1

T3

2601

full_word

4436742

1

T1

1619

T2

1

T3

3558

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8386903	1			T1	6637		T2	2		T3	6159
auto[TlIntgErrCmd]	103	1			T98	2		T103	3		T104	7
auto[TlIntgErrData]	110	1			T98	5		T103	5		T104	5
auto[TlIntgErrBoth]	127	1			T98	3		T103	2		T104	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4625435

1

T1

5011

T2

1

T3

5276

auto[1]

3761808

1

T1

1626

T2

1

T3

883

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3579049	1			T1	4644		T2	1		T3	2595
auto[TlIntgErrNone]	partial	auto[1]	371136	1			T1	374		T3	6		T4	12
auto[TlIntgErrNone]	full_word	auto[0]	1046222	1			T1	367		T3	2681		T4	53
auto[TlIntgErrNone]	full_word	auto[1]	3390496	1			T1	1252		T2	1		T3	877
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T103	1		T104	2		T117	6
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T98	2		T103	1		T104	5
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T103	1		T117	1		T168	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T157	2		T170	1		T171	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T98	2		T103	2		T104	2
auto[TlIntgErrData]	partial	auto[1]	53	1			T98	3		T103	2		T104	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T168	1		T172	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T103	1		T173	1		T170	1
auto[TlIntgErrBoth]	partial	auto[0]	64	1			T98	1		T103	2		T104	5
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T98	1		T104	2		T117	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T157	1		T174	1		T175	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T98	1		T104	1		T174	1