Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	505151376	2991954	0	0
DepthKnown_A	505151376	505022815	0	0
RvalidKnown_A	505151376	505022815	0	0
WreadyKnown_A	505151376	505022815	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505151376	2991954	0	0
T3	102423	832	0	0
T4	14968	832	0	0
T5	47371	832	0	0
T6	178159	7485	0	0
T7	94188	0	0	0
T8	322422	10823	0	0
T9	25463	0	0	0
T10	11528	1663	0	0
T11	6928	0	0	0
T13	0	1663	0	0
T14	0	832	0	0
T15	0	5824	0	0
T23	3367	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505151376	505022815	0	0
T1	416878	416795	0	0
T2	845	778	0	0
T3	102423	102372	0	0
T4	14968	14914	0	0
T5	47371	47315	0	0
T6	178159	178152	0	0
T7	94188	94103	0	0
T8	322422	322415	0	0
T9	25463	25411	0	0
T10	11528	11431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505151376	505022815	0	0
T1	416878	416795	0	0
T2	845	778	0	0
T3	102423	102372	0	0
T4	14968	14914	0	0
T5	47371	47315	0	0
T6	178159	178152	0	0
T7	94188	94103	0	0
T8	322422	322415	0	0
T9	25463	25411	0	0
T10	11528	11431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505151376	505022815	0	0
T1	416878	416795	0	0
T2	845	778	0	0
T3	102423	102372	0	0
T4	14968	14914	0	0
T5	47371	47315	0	0
T6	178159	178152	0	0
T7	94188	94103	0	0
T8	322422	322415	0	0
T9	25463	25411	0	0
T10	11528	11431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	505151376	3423743	0	0
DepthKnown_A	505151376	505022815	0	0
RvalidKnown_A	505151376	505022815	0	0
WreadyKnown_A	505151376	505022815	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505151376	3423743	0	0
T3	102423	832	0	0
T4	14968	2661	0	0
T5	47371	3725	0	0
T6	178159	4992	0	0
T7	94188	0	0	0
T8	322422	22611	0	0
T9	25463	0	0	0
T10	11528	832	0	0
T11	6928	0	0	0
T13	0	832	0	0
T14	0	3728	0	0
T15	0	9409	0	0
T23	3367	469	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505151376	505022815	0	0
T1	416878	416795	0	0
T2	845	778	0	0
T3	102423	102372	0	0
T4	14968	14914	0	0
T5	47371	47315	0	0
T6	178159	178152	0	0
T7	94188	94103	0	0
T8	322422	322415	0	0
T9	25463	25411	0	0
T10	11528	11431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505151376	505022815	0	0
T1	416878	416795	0	0
T2	845	778	0	0
T3	102423	102372	0	0
T4	14968	14914	0	0
T5	47371	47315	0	0
T6	178159	178152	0	0
T7	94188	94103	0	0
T8	322422	322415	0	0
T9	25463	25411	0	0
T10	11528	11431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505151376	505022815	0	0
T1	416878	416795	0	0
T2	845	778	0	0
T3	102423	102372	0	0
T4	14968	14914	0	0
T5	47371	47315	0	0
T6	178159	178152	0	0
T7	94188	94103	0	0
T8	322422	322415	0	0
T9	25463	25411	0	0
T10	11528	11431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	505151376	188078	0	0
DepthKnown_A	505151376	505022815	0	0
RvalidKnown_A	505151376	505022815	0	0
WreadyKnown_A	505151376	505022815	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505151376	188078	0	0
T1	416878	286	0	0
T2	845	0	0	0
T3	102423	0	0	0
T4	14968	0	0	0
T5	47371	0	0	0
T6	178159	1164	0	0
T7	94188	0	0	0
T8	322422	1416	0	0
T9	25463	125	0	0
T10	11528	0	0	0
T15	0	64	0	0
T23	0	100	0	0
T26	0	279	0	0
T27	0	960	0	0
T42	0	348	0	0
T43	0	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505151376	505022815	0	0
T1	416878	416795	0	0
T2	845	778	0	0
T3	102423	102372	0	0
T4	14968	14914	0	0
T5	47371	47315	0	0
T6	178159	178152	0	0
T7	94188	94103	0	0
T8	322422	322415	0	0
T9	25463	25411	0	0
T10	11528	11431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505151376	505022815	0	0
T1	416878	416795	0	0
T2	845	778	0	0
T3	102423	102372	0	0
T4	14968	14914	0	0
T5	47371	47315	0	0
T6	178159	178152	0	0
T7	94188	94103	0	0
T8	322422	322415	0	0
T9	25463	25411	0	0
T10	11528	11431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505151376	505022815	0	0
T1	416878	416795	0	0
T2	845	778	0	0
T3	102423	102372	0	0
T4	14968	14914	0	0
T5	47371	47315	0	0
T6	178159	178152	0	0
T7	94188	94103	0	0
T8	322422	322415	0	0
T9	25463	25411	0	0
T10	11528	11431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	505151376	450594	0	0
DepthKnown_A	505151376	505022815	0	0
RvalidKnown_A	505151376	505022815	0	0
WreadyKnown_A	505151376	505022815	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505151376	450594	0	0
T1	416878	286	0	0
T2	845	0	0	0
T3	102423	0	0	0
T4	14968	0	0	0
T5	47371	0	0	0
T6	178159	1164	0	0
T7	94188	0	0	0
T8	322422	6380	0	0
T9	25463	125	0	0
T10	11528	0	0	0
T15	0	219	0	0
T23	0	428	0	0
T26	0	1318	0	0
T27	0	2688	0	0
T42	0	1505	0	0
T43	0	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505151376	505022815	0	0
T1	416878	416795	0	0
T2	845	778	0	0
T3	102423	102372	0	0
T4	14968	14914	0	0
T5	47371	47315	0	0
T6	178159	178152	0	0
T7	94188	94103	0	0
T8	322422	322415	0	0
T9	25463	25411	0	0
T10	11528	11431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505151376	505022815	0	0
T1	416878	416795	0	0
T2	845	778	0	0
T3	102423	102372	0	0
T4	14968	14914	0	0
T5	47371	47315	0	0
T6	178159	178152	0	0
T7	94188	94103	0	0
T8	322422	322415	0	0
T9	25463	25411	0	0
T10	11528	11431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505151376	505022815	0	0
T1	416878	416795	0	0
T2	845	778	0	0
T3	102423	102372	0	0
T4	14968	14914	0	0
T5	47371	47315	0	0
T6	178159	178152	0	0
T7	94188	94103	0	0
T8	322422	322415	0	0
T9	25463	25411	0	0
T10	11528	11431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	505151376	6663912	0	0
DepthKnown_A	505151376	505022815	0	0
RvalidKnown_A	505151376	505022815	0	0
WreadyKnown_A	505151376	505022815	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505151376	6663912	0	0
T1	416878	6356	0	0
T2	845	2	0	0
T3	102423	5328	0	0
T4	14968	157	0	0
T5	47371	1724	0	0
T6	178159	34082	0	0
T7	94188	487	0	0
T8	322422	64105	0	0
T9	25463	567	0	0
T10	11528	375	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505151376	505022815	0	0
T1	416878	416795	0	0
T2	845	778	0	0
T3	102423	102372	0	0
T4	14968	14914	0	0
T5	47371	47315	0	0
T6	178159	178152	0	0
T7	94188	94103	0	0
T8	322422	322415	0	0
T9	25463	25411	0	0
T10	11528	11431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505151376	505022815	0	0
T1	416878	416795	0	0
T2	845	778	0	0
T3	102423	102372	0	0
T4	14968	14914	0	0
T5	47371	47315	0	0
T6	178159	178152	0	0
T7	94188	94103	0	0
T8	322422	322415	0	0
T9	25463	25411	0	0
T10	11528	11431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505151376	505022815	0	0
T1	416878	416795	0	0
T2	845	778	0	0
T3	102423	102372	0	0
T4	14968	14914	0	0
T5	47371	47315	0	0
T6	178159	178152	0	0
T7	94188	94103	0	0
T8	322422	322415	0	0
T9	25463	25411	0	0
T10	11528	11431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	505151376	14606924	0	0
DepthKnown_A	505151376	505022815	0	0
RvalidKnown_A	505151376	505022815	0	0
WreadyKnown_A	505151376	505022815	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505151376	14606924	0	0
T1	416878	6351	0	0
T2	845	13	0	0
T3	102423	5327	0	0
T4	14968	510	0	0
T5	47371	7394	0	0
T6	178159	33879	0	0
T7	94188	487	0	0
T8	322422	254765	0	0
T9	25463	564	0	0
T10	11528	1482	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505151376	505022815	0	0
T1	416878	416795	0	0
T2	845	778	0	0
T3	102423	102372	0	0
T4	14968	14914	0	0
T5	47371	47315	0	0
T6	178159	178152	0	0
T7	94188	94103	0	0
T8	322422	322415	0	0
T9	25463	25411	0	0
T10	11528	11431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505151376	505022815	0	0
T1	416878	416795	0	0
T2	845	778	0	0
T3	102423	102372	0	0
T4	14968	14914	0	0
T5	47371	47315	0	0
T6	178159	178152	0	0
T7	94188	94103	0	0
T8	322422	322415	0	0
T9	25463	25411	0	0
T10	11528	11431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505151376	505022815	0	0
T1	416878	416795	0	0
T2	845	778	0	0
T3	102423	102372	0	0
T4	14968	14914	0	0
T5	47371	47315	0	0
T6	178159	178152	0	0
T7	94188	94103	0	0
T8	322422	322415	0	0
T9	25463	25411	0	0
T10	11528	11431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0