Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T8
1	0	Covered	T1,T6,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Unreachable
1	1	Covered	T1,T6,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T8,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T15
1	0	Covered	T6,T8,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Unreachable
1	1	Covered	T6,T8,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T8
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	804820351	652507436	0	0
CheckNGreaterZero_A	2925	2925	0	0
GntImpliesReady_A	804820351	3804619	0	0
GntImpliesValid_A	804820351	3804619	0	0
GrantKnown_A	804820351	652507436	0	0
IdxKnown_A	804820351	652507436	0	0
IndexIsCorrect_A	804820351	3804619	0	0
LockArbDecision_A	804820351	0	0	0
NoReadyValidNoGrant_A	804820351	0	0	0
ReadyAndValidImplyGrant_A	804820351	3804619	0	0
ReqAndReadyImplyGrant_A	804820351	3804619	0	0
ReqImpliesValid_A	804820351	3804619	0	0
ReqStaysHighUntilGranted0_M	804820351	0	0	0
RoundRobin_A	804820351	2	0	975
ValidKnown_A	804820351	652507436	0	0
gen_data_port_assertion.DataFlow_A	804820351	3804619	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804820351	652507436	0	0
T1	469415	467827	0	0
T2	845	778	0	0
T3	129623	115972	0	0
T4	47088	30776	0	0
T5	84053	65656	0	0
T6	879545	525000	0	0
T7	214120	149695	0	0
T8	1122726	715844	0	0
T9	65535	45171	0	0
T10	56590	33303	0	0
T13	103098	51080	0	0
T14	16513	16304	0	0
T15	0	438658	0	0
T16	0	64416	0	0
T27	0	68696	0	0
T29	0	936	0	0
T30	0	34192	0	0
T31	0	81312	0	0
T33	0	384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2925	2925	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804820351	3804619	0	0
T1	469415	2937	0	0
T2	845	0	0	0
T3	116023	832	0	0
T4	31028	832	0	0
T5	65712	832	0	0
T6	879545	16222	0	0
T7	214120	0	0	0
T8	1122726	22194	0	0
T9	65535	653	0	0
T10	56590	832	0	0
T13	103098	832	0	0
T14	16513	0	0	0
T15	439548	1793	0	0
T16	64416	0	0	0
T17	0	1424	0	0
T23	0	200	0	0
T26	533995	1522	0	0
T27	0	8777	0	0
T33	0	43	0	0
T42	0	2197	0	0
T43	0	260	0	0
T45	0	12066	0	0
T51	0	5314	0	0
T56	0	3444	0	0
T57	0	3866	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804820351	3804619	0	0
T1	469415	2937	0	0
T2	845	0	0	0
T3	116023	832	0	0
T4	31028	832	0	0
T5	65712	832	0	0
T6	879545	16222	0	0
T7	214120	0	0	0
T8	1122726	22194	0	0
T9	65535	653	0	0
T10	56590	832	0	0
T13	103098	832	0	0
T14	16513	0	0	0
T15	439548	1793	0	0
T16	64416	0	0	0
T17	0	1424	0	0
T23	0	200	0	0
T26	533995	1522	0	0
T27	0	8777	0	0
T33	0	43	0	0
T42	0	2197	0	0
T43	0	260	0	0
T45	0	12066	0	0
T51	0	5314	0	0
T56	0	3444	0	0
T57	0	3866	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804820351	652507436	0	0
T1	469415	467827	0	0
T2	845	778	0	0
T3	129623	115972	0	0
T4	47088	30776	0	0
T5	84053	65656	0	0
T6	879545	525000	0	0
T7	214120	149695	0	0
T8	1122726	715844	0	0
T9	65535	45171	0	0
T10	56590	33303	0	0
T13	103098	51080	0	0
T14	16513	16304	0	0
T15	0	438658	0	0
T16	0	64416	0	0
T27	0	68696	0	0
T29	0	936	0	0
T30	0	34192	0	0
T31	0	81312	0	0
T33	0	384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804820351	652507436	0	0
T1	469415	467827	0	0
T2	845	778	0	0
T3	129623	115972	0	0
T4	47088	30776	0	0
T5	84053	65656	0	0
T6	879545	525000	0	0
T7	214120	149695	0	0
T8	1122726	715844	0	0
T9	65535	45171	0	0
T10	56590	33303	0	0
T13	103098	51080	0	0
T14	16513	16304	0	0
T15	0	438658	0	0
T16	0	64416	0	0
T27	0	68696	0	0
T29	0	936	0	0
T30	0	34192	0	0
T31	0	81312	0	0
T33	0	384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804820351	3804619	0	0
T1	469415	2937	0	0
T2	845	0	0	0
T3	116023	832	0	0
T4	31028	832	0	0
T5	65712	832	0	0
T6	879545	16222	0	0
T7	214120	0	0	0
T8	1122726	22194	0	0
T9	65535	653	0	0
T10	56590	832	0	0
T13	103098	832	0	0
T14	16513	0	0	0
T15	439548	1793	0	0
T16	64416	0	0	0
T17	0	1424	0	0
T23	0	200	0	0
T26	533995	1522	0	0
T27	0	8777	0	0
T33	0	43	0	0
T42	0	2197	0	0
T43	0	260	0	0
T45	0	12066	0	0
T51	0	5314	0	0
T56	0	3444	0	0
T57	0	3866	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804820351	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804820351	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804820351	3804619	0	0
T1	469415	2937	0	0
T2	845	0	0	0
T3	116023	832	0	0
T4	31028	832	0	0
T5	65712	832	0	0
T6	879545	16222	0	0
T7	214120	0	0	0
T8	1122726	22194	0	0
T9	65535	653	0	0
T10	56590	832	0	0
T13	103098	832	0	0
T14	16513	0	0	0
T15	439548	1793	0	0
T16	64416	0	0	0
T17	0	1424	0	0
T23	0	200	0	0
T26	533995	1522	0	0
T27	0	8777	0	0
T33	0	43	0	0
T42	0	2197	0	0
T43	0	260	0	0
T45	0	12066	0	0
T51	0	5314	0	0
T56	0	3444	0	0
T57	0	3866	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804820351	3804619	0	0
T1	469415	2937	0	0
T2	845	0	0	0
T3	116023	832	0	0
T4	31028	832	0	0
T5	65712	832	0	0
T6	879545	16222	0	0
T7	214120	0	0	0
T8	1122726	22194	0	0
T9	65535	653	0	0
T10	56590	832	0	0
T13	103098	832	0	0
T14	16513	0	0	0
T15	439548	1793	0	0
T16	64416	0	0	0
T17	0	1424	0	0
T23	0	200	0	0
T26	533995	1522	0	0
T27	0	8777	0	0
T33	0	43	0	0
T42	0	2197	0	0
T43	0	260	0	0
T45	0	12066	0	0
T51	0	5314	0	0
T56	0	3444	0	0
T57	0	3866	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804820351	3804619	0	0
T1	469415	2937	0	0
T2	845	0	0	0
T3	116023	832	0	0
T4	31028	832	0	0
T5	65712	832	0	0
T6	879545	16222	0	0
T7	214120	0	0	0
T8	1122726	22194	0	0
T9	65535	653	0	0
T10	56590	832	0	0
T13	103098	832	0	0
T14	16513	0	0	0
T15	439548	1793	0	0
T16	64416	0	0	0
T17	0	1424	0	0
T23	0	200	0	0
T26	533995	1522	0	0
T27	0	8777	0	0
T33	0	43	0	0
T42	0	2197	0	0
T43	0	260	0	0
T45	0	12066	0	0
T51	0	5314	0	0
T56	0	3444	0	0
T57	0	3866	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	804820351	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804820351	2	0	975
T19	364580	2	0	1
T58	119560	0	0	1
T59	106788	0	0	1
T60	75985	0	0	1
T61	6595	0	0	1
T62	260948	0	0	1
T63	169640	0	0	1
T64	2999	0	0	1
T65	4926	0	0	1
T66	251501	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804820351	652507436	0	0
T1	469415	467827	0	0
T2	845	778	0	0
T3	129623	115972	0	0
T4	47088	30776	0	0
T5	84053	65656	0	0
T6	879545	525000	0	0
T7	214120	149695	0	0
T8	1122726	715844	0	0
T9	65535	45171	0	0
T10	56590	33303	0	0
T13	103098	51080	0	0
T14	16513	16304	0	0
T15	0	438658	0	0
T16	0	64416	0	0
T27	0	68696	0	0
T29	0	936	0	0
T30	0	34192	0	0
T31	0	81312	0	0
T33	0	384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804820351	3804619	0	0
T1	469415	2937	0	0
T2	845	0	0	0
T3	116023	832	0	0
T4	31028	832	0	0
T5	65712	832	0	0
T6	879545	16222	0	0
T7	214120	0	0	0
T8	1122726	22194	0	0
T9	65535	653	0	0
T10	56590	832	0	0
T13	103098	832	0	0
T14	16513	0	0	0
T15	439548	1793	0	0
T16	64416	0	0	0
T17	0	1424	0	0
T23	0	200	0	0
T26	533995	1522	0	0
T27	0	8777	0	0
T33	0	43	0	0
T42	0	2197	0	0
T43	0	260	0	0
T45	0	12066	0	0
T51	0	5314	0	0
T56	0	3444	0	0
T57	0	3866	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T8
1	0	Covered	T1,T6,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Unreachable
1	1	Covered	T1,T6,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T6,T8
0	0	1	Unreachable
0	0	0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	150920950	23940067	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	150920950	561776	0	0
GntImpliesValid_A	150920950	561776	0	0
GrantKnown_A	150920950	23940067	0	0
IdxKnown_A	150920950	23940067	0	0
IndexIsCorrect_A	150920950	561776	0	0
LockArbDecision_A	150920950	0	0	0
NoReadyValidNoGrant_A	150920950	0	0	0
ReadyAndValidImplyGrant_A	150920950	561776	0	0
ReqAndReadyImplyGrant_A	150920950	561776	0	0
ReqImpliesValid_A	150920950	561776	0	0
ReqStaysHighUntilGranted0_M	150920950	0	0	0
RoundRobin_A	150920950	0	0	0
ValidKnown_A	150920950	23940067	0	0
gen_data_port_assertion.DataFlow_A	150920950	561776	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150920950	23940067	0	0
T1	52537	51032	0	0
T3	13600	0	0	0
T4	16060	0	0	0
T5	18341	0	0	0
T6	350693	101960	0	0
T7	59966	55592	0	0
T8	400152	89736	0	0
T9	20036	19760	0	0
T10	22531	0	0	0
T13	51549	0	0	0
T27	0	68696	0	0
T29	0	936	0	0
T30	0	34192	0	0
T31	0	81312	0	0
T33	0	384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150920950	561776	0	0
T1	52537	1917	0	0
T3	13600	0	0	0
T4	16060	0	0	0
T5	18341	0	0	0
T6	350693	4475	0	0
T7	59966	0	0	0
T8	400152	4013	0	0
T9	20036	505	0	0
T10	22531	0	0	0
T13	51549	0	0	0
T17	0	1424	0	0
T27	0	3170	0	0
T33	0	43	0	0
T51	0	5314	0	0
T56	0	3444	0	0
T57	0	3866	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150920950	561776	0	0
T1	52537	1917	0	0
T3	13600	0	0	0
T4	16060	0	0	0
T5	18341	0	0	0
T6	350693	4475	0	0
T7	59966	0	0	0
T8	400152	4013	0	0
T9	20036	505	0	0
T10	22531	0	0	0
T13	51549	0	0	0
T17	0	1424	0	0
T27	0	3170	0	0
T33	0	43	0	0
T51	0	5314	0	0
T56	0	3444	0	0
T57	0	3866	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150920950	23940067	0	0
T1	52537	51032	0	0
T3	13600	0	0	0
T4	16060	0	0	0
T5	18341	0	0	0
T6	350693	101960	0	0
T7	59966	55592	0	0
T8	400152	89736	0	0
T9	20036	19760	0	0
T10	22531	0	0	0
T13	51549	0	0	0
T27	0	68696	0	0
T29	0	936	0	0
T30	0	34192	0	0
T31	0	81312	0	0
T33	0	384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150920950	23940067	0	0
T1	52537	51032	0	0
T3	13600	0	0	0
T4	16060	0	0	0
T5	18341	0	0	0
T6	350693	101960	0	0
T7	59966	55592	0	0
T8	400152	89736	0	0
T9	20036	19760	0	0
T10	22531	0	0	0
T13	51549	0	0	0
T27	0	68696	0	0
T29	0	936	0	0
T30	0	34192	0	0
T31	0	81312	0	0
T33	0	384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150920950	561776	0	0
T1	52537	1917	0	0
T3	13600	0	0	0
T4	16060	0	0	0
T5	18341	0	0	0
T6	350693	4475	0	0
T7	59966	0	0	0
T8	400152	4013	0	0
T9	20036	505	0	0
T10	22531	0	0	0
T13	51549	0	0	0
T17	0	1424	0	0
T27	0	3170	0	0
T33	0	43	0	0
T51	0	5314	0	0
T56	0	3444	0	0
T57	0	3866	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150920950	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150920950	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150920950	561776	0	0
T1	52537	1917	0	0
T3	13600	0	0	0
T4	16060	0	0	0
T5	18341	0	0	0
T6	350693	4475	0	0
T7	59966	0	0	0
T8	400152	4013	0	0
T9	20036	505	0	0
T10	22531	0	0	0
T13	51549	0	0	0
T17	0	1424	0	0
T27	0	3170	0	0
T33	0	43	0	0
T51	0	5314	0	0
T56	0	3444	0	0
T57	0	3866	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150920950	561776	0	0
T1	52537	1917	0	0
T3	13600	0	0	0
T4	16060	0	0	0
T5	18341	0	0	0
T6	350693	4475	0	0
T7	59966	0	0	0
T8	400152	4013	0	0
T9	20036	505	0	0
T10	22531	0	0	0
T13	51549	0	0	0
T17	0	1424	0	0
T27	0	3170	0	0
T33	0	43	0	0
T51	0	5314	0	0
T56	0	3444	0	0
T57	0	3866	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150920950	561776	0	0
T1	52537	1917	0	0
T3	13600	0	0	0
T4	16060	0	0	0
T5	18341	0	0	0
T6	350693	4475	0	0
T7	59966	0	0	0
T8	400152	4013	0	0
T9	20036	505	0	0
T10	22531	0	0	0
T13	51549	0	0	0
T17	0	1424	0	0
T27	0	3170	0	0
T33	0	43	0	0
T51	0	5314	0	0
T56	0	3444	0	0
T57	0	3866	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	150920950	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150920950	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150920950	23940067	0	0
T1	52537	51032	0	0
T3	13600	0	0	0
T4	16060	0	0	0
T5	18341	0	0	0
T6	350693	101960	0	0
T7	59966	55592	0	0
T8	400152	89736	0	0
T9	20036	19760	0	0
T10	22531	0	0	0
T13	51549	0	0	0
T27	0	68696	0	0
T29	0	936	0	0
T30	0	34192	0	0
T31	0	81312	0	0
T33	0	384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150920950	561776	0	0
T1	52537	1917	0	0
T3	13600	0	0	0
T4	16060	0	0	0
T5	18341	0	0	0
T6	350693	4475	0	0
T7	59966	0	0	0
T8	400152	4013	0	0
T9	20036	505	0	0
T10	22531	0	0	0
T13	51549	0	0	0
T17	0	1424	0	0
T27	0	3170	0	0
T33	0	43	0	0
T51	0	5314	0	0
T56	0	3444	0	0
T57	0	3866	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T8,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T15
1	0	Covered	T6,T8,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Unreachable
1	1	Covered	T6,T8,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T8,T15
0	0	1	Unreachable
0	0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	150920950	125676970	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	150920950	936223	0	0
GntImpliesValid_A	150920950	936223	0	0
GrantKnown_A	150920950	125676970	0	0
IdxKnown_A	150920950	125676970	0	0
IndexIsCorrect_A	150920950	936223	0	0
LockArbDecision_A	150920950	0	0	0
NoReadyValidNoGrant_A	150920950	0	0	0
ReadyAndValidImplyGrant_A	150920950	936223	0	0
ReqAndReadyImplyGrant_A	150920950	936223	0	0
ReqImpliesValid_A	150920950	936223	0	0
ReqStaysHighUntilGranted0_M	150920950	0	0	0
RoundRobin_A	150920950	0	0	0
ValidKnown_A	150920950	125676970	0	0
gen_data_port_assertion.DataFlow_A	150920950	936223	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150920950	125676970	0	0
T3	13600	13600	0	0
T4	16060	15862	0	0
T5	18341	18341	0	0
T6	350693	244888	0	0
T7	59966	0	0	0
T8	400152	303693	0	0
T9	20036	0	0	0
T10	22531	21872	0	0
T13	51549	51080	0	0
T14	16513	16304	0	0
T15	0	438658	0	0
T16	0	64416	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150920950	936223	0	0
T6	350693	4105	0	0
T7	59966	0	0	0
T8	400152	8066	0	0
T9	20036	0	0	0
T10	22531	0	0	0
T13	51549	0	0	0
T14	16513	0	0	0
T15	439548	1793	0	0
T16	64416	0	0	0
T26	533995	1522	0	0
T27	0	5607	0	0
T42	0	2197	0	0
T43	0	260	0	0
T45	0	12066	0	0
T46	0	649	0	0
T67	0	1644	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150920950	936223	0	0
T6	350693	4105	0	0
T7	59966	0	0	0
T8	400152	8066	0	0
T9	20036	0	0	0
T10	22531	0	0	0
T13	51549	0	0	0
T14	16513	0	0	0
T15	439548	1793	0	0
T16	64416	0	0	0
T26	533995	1522	0	0
T27	0	5607	0	0
T42	0	2197	0	0
T43	0	260	0	0
T45	0	12066	0	0
T46	0	649	0	0
T67	0	1644	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150920950	125676970	0	0
T3	13600	13600	0	0
T4	16060	15862	0	0
T5	18341	18341	0	0
T6	350693	244888	0	0
T7	59966	0	0	0
T8	400152	303693	0	0
T9	20036	0	0	0
T10	22531	21872	0	0
T13	51549	51080	0	0
T14	16513	16304	0	0
T15	0	438658	0	0
T16	0	64416	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150920950	125676970	0	0
T3	13600	13600	0	0
T4	16060	15862	0	0
T5	18341	18341	0	0
T6	350693	244888	0	0
T7	59966	0	0	0
T8	400152	303693	0	0
T9	20036	0	0	0
T10	22531	21872	0	0
T13	51549	51080	0	0
T14	16513	16304	0	0
T15	0	438658	0	0
T16	0	64416	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150920950	936223	0	0
T6	350693	4105	0	0
T7	59966	0	0	0
T8	400152	8066	0	0
T9	20036	0	0	0
T10	22531	0	0	0
T13	51549	0	0	0
T14	16513	0	0	0
T15	439548	1793	0	0
T16	64416	0	0	0
T26	533995	1522	0	0
T27	0	5607	0	0
T42	0	2197	0	0
T43	0	260	0	0
T45	0	12066	0	0
T46	0	649	0	0
T67	0	1644	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150920950	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150920950	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150920950	936223	0	0
T6	350693	4105	0	0
T7	59966	0	0	0
T8	400152	8066	0	0
T9	20036	0	0	0
T10	22531	0	0	0
T13	51549	0	0	0
T14	16513	0	0	0
T15	439548	1793	0	0
T16	64416	0	0	0
T26	533995	1522	0	0
T27	0	5607	0	0
T42	0	2197	0	0
T43	0	260	0	0
T45	0	12066	0	0
T46	0	649	0	0
T67	0	1644	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150920950	936223	0	0
T6	350693	4105	0	0
T7	59966	0	0	0
T8	400152	8066	0	0
T9	20036	0	0	0
T10	22531	0	0	0
T13	51549	0	0	0
T14	16513	0	0	0
T15	439548	1793	0	0
T16	64416	0	0	0
T26	533995	1522	0	0
T27	0	5607	0	0
T42	0	2197	0	0
T43	0	260	0	0
T45	0	12066	0	0
T46	0	649	0	0
T67	0	1644	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150920950	936223	0	0
T6	350693	4105	0	0
T7	59966	0	0	0
T8	400152	8066	0	0
T9	20036	0	0	0
T10	22531	0	0	0
T13	51549	0	0	0
T14	16513	0	0	0
T15	439548	1793	0	0
T16	64416	0	0	0
T26	533995	1522	0	0
T27	0	5607	0	0
T42	0	2197	0	0
T43	0	260	0	0
T45	0	12066	0	0
T46	0	649	0	0
T67	0	1644	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	150920950	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150920950	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150920950	125676970	0	0
T3	13600	13600	0	0
T4	16060	15862	0	0
T5	18341	18341	0	0
T6	350693	244888	0	0
T7	59966	0	0	0
T8	400152	303693	0	0
T9	20036	0	0	0
T10	22531	21872	0	0
T13	51549	51080	0	0
T14	16513	16304	0	0
T15	0	438658	0	0
T16	0	64416	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150920950	936223	0	0
T6	350693	4105	0	0
T7	59966	0	0	0
T8	400152	8066	0	0
T9	20036	0	0	0
T10	22531	0	0	0
T13	51549	0	0	0
T14	16513	0	0	0
T15	439548	1793	0	0
T16	64416	0	0	0
T26	533995	1522	0	0
T27	0	5607	0	0
T42	0	2197	0	0
T43	0	260	0	0
T45	0	12066	0	0
T46	0	649	0	0
T67	0	1644	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T8
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	502978451	502890399	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	502978451	2306620	0	0
GntImpliesValid_A	502978451	2306620	0	0
GrantKnown_A	502978451	502890399	0	0
IdxKnown_A	502978451	502890399	0	0
IndexIsCorrect_A	502978451	2306620	0	0
LockArbDecision_A	502978451	0	0	0
NoReadyValidNoGrant_A	502978451	0	0	0
ReadyAndValidImplyGrant_A	502978451	2306620	0	0
ReqAndReadyImplyGrant_A	502978451	2306620	0	0
ReqImpliesValid_A	502978451	2306620	0	0
ReqStaysHighUntilGranted0_M	502978451	0	0	0
RoundRobin_A	502978451	2	0	975
ValidKnown_A	502978451	502890399	0	0
gen_data_port_assertion.DataFlow_A	502978451	2306620	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502978451	502890399	0	0
T1	416878	416795	0	0
T2	845	778	0	0
T3	102423	102372	0	0
T4	14968	14914	0	0
T5	47371	47315	0	0
T6	178159	178152	0	0
T7	94188	94103	0	0
T8	322422	322415	0	0
T9	25463	25411	0	0
T10	11528	11431	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502978451	2306620	0	0
T1	416878	1020	0	0
T2	845	0	0	0
T3	102423	832	0	0
T4	14968	832	0	0
T5	47371	832	0	0
T6	178159	7642	0	0
T7	94188	0	0	0
T8	322422	10115	0	0
T9	25463	148	0	0
T10	11528	832	0	0
T13	0	832	0	0
T23	0	200	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502978451	2306620	0	0
T1	416878	1020	0	0
T2	845	0	0	0
T3	102423	832	0	0
T4	14968	832	0	0
T5	47371	832	0	0
T6	178159	7642	0	0
T7	94188	0	0	0
T8	322422	10115	0	0
T9	25463	148	0	0
T10	11528	832	0	0
T13	0	832	0	0
T23	0	200	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502978451	502890399	0	0
T1	416878	416795	0	0
T2	845	778	0	0
T3	102423	102372	0	0
T4	14968	14914	0	0
T5	47371	47315	0	0
T6	178159	178152	0	0
T7	94188	94103	0	0
T8	322422	322415	0	0
T9	25463	25411	0	0
T10	11528	11431	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502978451	502890399	0	0
T1	416878	416795	0	0
T2	845	778	0	0
T3	102423	102372	0	0
T4	14968	14914	0	0
T5	47371	47315	0	0
T6	178159	178152	0	0
T7	94188	94103	0	0
T8	322422	322415	0	0
T9	25463	25411	0	0
T10	11528	11431	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502978451	2306620	0	0
T1	416878	1020	0	0
T2	845	0	0	0
T3	102423	832	0	0
T4	14968	832	0	0
T5	47371	832	0	0
T6	178159	7642	0	0
T7	94188	0	0	0
T8	322422	10115	0	0
T9	25463	148	0	0
T10	11528	832	0	0
T13	0	832	0	0
T23	0	200	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502978451	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502978451	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502978451	2306620	0	0
T1	416878	1020	0	0
T2	845	0	0	0
T3	102423	832	0	0
T4	14968	832	0	0
T5	47371	832	0	0
T6	178159	7642	0	0
T7	94188	0	0	0
T8	322422	10115	0	0
T9	25463	148	0	0
T10	11528	832	0	0
T13	0	832	0	0
T23	0	200	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502978451	2306620	0	0
T1	416878	1020	0	0
T2	845	0	0	0
T3	102423	832	0	0
T4	14968	832	0	0
T5	47371	832	0	0
T6	178159	7642	0	0
T7	94188	0	0	0
T8	322422	10115	0	0
T9	25463	148	0	0
T10	11528	832	0	0
T13	0	832	0	0
T23	0	200	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502978451	2306620	0	0
T1	416878	1020	0	0
T2	845	0	0	0
T3	102423	832	0	0
T4	14968	832	0	0
T5	47371	832	0	0
T6	178159	7642	0	0
T7	94188	0	0	0
T8	322422	10115	0	0
T9	25463	148	0	0
T10	11528	832	0	0
T13	0	832	0	0
T23	0	200	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	502978451	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502978451	2	0	975
T19	364580	2	0	1
T58	119560	0	0	1
T59	106788	0	0	1
T60	75985	0	0	1
T61	6595	0	0	1
T62	260948	0	0	1
T63	169640	0	0	1
T64	2999	0	0	1
T65	4926	0	0	1
T66	251501	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502978451	502890399	0	0
T1	416878	416795	0	0
T2	845	778	0	0
T3	102423	102372	0	0
T4	14968	14914	0	0
T5	47371	47315	0	0
T6	178159	178152	0	0
T7	94188	94103	0	0
T8	322422	322415	0	0
T9	25463	25411	0	0
T10	11528	11431	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502978451	2306620	0	0
T1	416878	1020	0	0
T2	845	0	0	0
T3	102423	832	0	0
T4	14968	832	0	0
T5	47371	832	0	0
T6	178159	7642	0	0
T7	94188	0	0	0
T8	322422	10115	0	0
T9	25463	148	0	0
T10	11528	832	0	0
T13	0	832	0	0
T23	0	200	0	0