Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
3309 |
0 |
0 |
T98 |
9729 |
2 |
0 |
0 |
T99 |
15490 |
8 |
0 |
0 |
T100 |
12365 |
5 |
0 |
0 |
T101 |
21071 |
258 |
0 |
0 |
T102 |
8632 |
312 |
0 |
0 |
T103 |
35043 |
3 |
0 |
0 |
T104 |
19411 |
4 |
0 |
0 |
T111 |
5363 |
20 |
0 |
0 |
T117 |
53472 |
2 |
0 |
0 |
T118 |
5611 |
1 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
2227 |
0 |
0 |
T99 |
15490 |
22 |
0 |
0 |
T103 |
35043 |
46 |
0 |
0 |
T118 |
5611 |
16 |
0 |
0 |
T120 |
180533 |
438 |
0 |
0 |
T125 |
68708 |
296 |
0 |
0 |
T126 |
7154 |
5 |
0 |
0 |
T145 |
4101 |
4 |
0 |
0 |
T155 |
39006 |
277 |
0 |
0 |
T156 |
9827 |
3 |
0 |
0 |
T157 |
66546 |
64 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
2210 |
0 |
0 |
T99 |
15490 |
27 |
0 |
0 |
T103 |
35043 |
32 |
0 |
0 |
T105 |
11501 |
3 |
0 |
0 |
T118 |
5611 |
9 |
0 |
0 |
T120 |
180533 |
450 |
0 |
0 |
T125 |
68708 |
307 |
0 |
0 |
T126 |
7154 |
11 |
0 |
0 |
T145 |
4101 |
6 |
0 |
0 |
T155 |
39006 |
261 |
0 |
0 |
T157 |
66546 |
72 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
2454 |
0 |
0 |
T99 |
15490 |
41 |
0 |
0 |
T103 |
35043 |
87 |
0 |
0 |
T118 |
5611 |
19 |
0 |
0 |
T120 |
180533 |
385 |
0 |
0 |
T125 |
68708 |
229 |
0 |
0 |
T126 |
7154 |
19 |
0 |
0 |
T145 |
4101 |
9 |
0 |
0 |
T155 |
39006 |
313 |
0 |
0 |
T156 |
9827 |
9 |
0 |
0 |
T157 |
66546 |
178 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
7948 |
0 |
0 |
T99 |
15490 |
480 |
0 |
0 |
T103 |
35043 |
581 |
0 |
0 |
T118 |
5611 |
7 |
0 |
0 |
T120 |
180533 |
453 |
0 |
0 |
T125 |
68708 |
312 |
0 |
0 |
T126 |
7154 |
271 |
0 |
0 |
T145 |
4101 |
138 |
0 |
0 |
T155 |
39006 |
225 |
0 |
0 |
T156 |
9827 |
14 |
0 |
0 |
T157 |
66546 |
1281 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
7845 |
0 |
0 |
T99 |
15490 |
324 |
0 |
0 |
T103 |
35043 |
696 |
0 |
0 |
T120 |
180533 |
400 |
0 |
0 |
T125 |
68708 |
296 |
0 |
0 |
T126 |
7154 |
9 |
0 |
0 |
T145 |
4101 |
120 |
0 |
0 |
T155 |
39006 |
305 |
0 |
0 |
T156 |
9827 |
114 |
0 |
0 |
T157 |
66546 |
1567 |
0 |
0 |
T158 |
14646 |
108 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
7616 |
0 |
0 |
T99 |
15490 |
267 |
0 |
0 |
T103 |
35043 |
701 |
0 |
0 |
T118 |
5611 |
143 |
0 |
0 |
T120 |
180533 |
438 |
0 |
0 |
T125 |
68708 |
307 |
0 |
0 |
T126 |
7154 |
140 |
0 |
0 |
T145 |
4101 |
126 |
0 |
0 |
T155 |
39006 |
275 |
0 |
0 |
T156 |
9827 |
74 |
0 |
0 |
T157 |
66546 |
739 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
7711 |
0 |
0 |
T99 |
15490 |
283 |
0 |
0 |
T103 |
35043 |
626 |
0 |
0 |
T118 |
5611 |
11 |
0 |
0 |
T120 |
180533 |
495 |
0 |
0 |
T125 |
68708 |
233 |
0 |
0 |
T126 |
7154 |
14 |
0 |
0 |
T145 |
4101 |
115 |
0 |
0 |
T155 |
39006 |
287 |
0 |
0 |
T156 |
9827 |
71 |
0 |
0 |
T157 |
66546 |
1432 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
7775 |
0 |
0 |
T99 |
15490 |
389 |
0 |
0 |
T103 |
35043 |
678 |
0 |
0 |
T118 |
5611 |
109 |
0 |
0 |
T120 |
180533 |
458 |
0 |
0 |
T125 |
68708 |
220 |
0 |
0 |
T126 |
7154 |
115 |
0 |
0 |
T145 |
4101 |
5 |
0 |
0 |
T155 |
39006 |
252 |
0 |
0 |
T156 |
9827 |
3 |
0 |
0 |
T157 |
66546 |
1541 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
7229 |
0 |
0 |
T99 |
15490 |
141 |
0 |
0 |
T103 |
35043 |
813 |
0 |
0 |
T118 |
5611 |
108 |
0 |
0 |
T120 |
180533 |
450 |
0 |
0 |
T125 |
68708 |
268 |
0 |
0 |
T126 |
7154 |
159 |
0 |
0 |
T145 |
4101 |
2 |
0 |
0 |
T155 |
39006 |
264 |
0 |
0 |
T156 |
9827 |
66 |
0 |
0 |
T157 |
66546 |
1332 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
6498 |
0 |
0 |
T99 |
15490 |
144 |
0 |
0 |
T101 |
21071 |
4 |
0 |
0 |
T103 |
35043 |
505 |
0 |
0 |
T118 |
5611 |
4 |
0 |
0 |
T120 |
180533 |
462 |
0 |
0 |
T125 |
68708 |
344 |
0 |
0 |
T126 |
7154 |
15 |
0 |
0 |
T145 |
4101 |
1 |
0 |
0 |
T155 |
39006 |
270 |
0 |
0 |
T156 |
9827 |
64 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
7069 |
0 |
0 |
T99 |
15490 |
30 |
0 |
0 |
T103 |
35043 |
518 |
0 |
0 |
T118 |
5611 |
110 |
0 |
0 |
T120 |
180533 |
465 |
0 |
0 |
T125 |
68708 |
297 |
0 |
0 |
T126 |
7154 |
9 |
0 |
0 |
T145 |
4101 |
9 |
0 |
0 |
T155 |
39006 |
300 |
0 |
0 |
T156 |
9827 |
10 |
0 |
0 |
T157 |
66546 |
1073 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
4481 |
0 |
0 |
T99 |
15490 |
188 |
0 |
0 |
T103 |
35043 |
400 |
0 |
0 |
T118 |
5611 |
7 |
0 |
0 |
T120 |
180533 |
469 |
0 |
0 |
T125 |
68708 |
280 |
0 |
0 |
T126 |
7154 |
46 |
0 |
0 |
T145 |
4101 |
3 |
0 |
0 |
T155 |
39006 |
261 |
0 |
0 |
T156 |
9827 |
14 |
0 |
0 |
T157 |
66546 |
573 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
4350 |
0 |
0 |
T99 |
15490 |
55 |
0 |
0 |
T103 |
35043 |
278 |
0 |
0 |
T118 |
5611 |
14 |
0 |
0 |
T120 |
180533 |
464 |
0 |
0 |
T125 |
68708 |
321 |
0 |
0 |
T126 |
7154 |
69 |
0 |
0 |
T145 |
4101 |
1 |
0 |
0 |
T155 |
39006 |
299 |
0 |
0 |
T156 |
9827 |
24 |
0 |
0 |
T157 |
66546 |
618 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
4238 |
0 |
0 |
T99 |
15490 |
80 |
0 |
0 |
T103 |
35043 |
296 |
0 |
0 |
T118 |
5611 |
40 |
0 |
0 |
T120 |
180533 |
448 |
0 |
0 |
T125 |
68708 |
267 |
0 |
0 |
T126 |
7154 |
1 |
0 |
0 |
T145 |
4101 |
61 |
0 |
0 |
T155 |
39006 |
298 |
0 |
0 |
T156 |
9827 |
43 |
0 |
0 |
T157 |
66546 |
445 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
4274 |
0 |
0 |
T99 |
15490 |
69 |
0 |
0 |
T103 |
35043 |
224 |
0 |
0 |
T118 |
5611 |
2 |
0 |
0 |
T120 |
180533 |
479 |
0 |
0 |
T125 |
68708 |
288 |
0 |
0 |
T126 |
7154 |
73 |
0 |
0 |
T145 |
4101 |
4 |
0 |
0 |
T155 |
39006 |
256 |
0 |
0 |
T156 |
9827 |
36 |
0 |
0 |
T157 |
66546 |
558 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
4298 |
0 |
0 |
T99 |
15490 |
110 |
0 |
0 |
T103 |
35043 |
251 |
0 |
0 |
T118 |
5611 |
45 |
0 |
0 |
T120 |
180533 |
480 |
0 |
0 |
T125 |
68708 |
313 |
0 |
0 |
T126 |
7154 |
38 |
0 |
0 |
T145 |
4101 |
6 |
0 |
0 |
T155 |
39006 |
219 |
0 |
0 |
T156 |
9827 |
45 |
0 |
0 |
T157 |
66546 |
411 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
4184 |
0 |
0 |
T99 |
15490 |
101 |
0 |
0 |
T103 |
35043 |
224 |
0 |
0 |
T118 |
5611 |
48 |
0 |
0 |
T120 |
180533 |
507 |
0 |
0 |
T125 |
68708 |
203 |
0 |
0 |
T126 |
7154 |
63 |
0 |
0 |
T145 |
4101 |
56 |
0 |
0 |
T155 |
39006 |
243 |
0 |
0 |
T156 |
9827 |
39 |
0 |
0 |
T157 |
66546 |
349 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
4115 |
0 |
0 |
T99 |
15490 |
103 |
0 |
0 |
T103 |
35043 |
305 |
0 |
0 |
T118 |
5611 |
4 |
0 |
0 |
T120 |
180533 |
459 |
0 |
0 |
T125 |
68708 |
276 |
0 |
0 |
T126 |
7154 |
102 |
0 |
0 |
T145 |
4101 |
58 |
0 |
0 |
T155 |
39006 |
300 |
0 |
0 |
T156 |
9827 |
8 |
0 |
0 |
T157 |
66546 |
384 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
4092 |
0 |
0 |
T99 |
15490 |
13 |
0 |
0 |
T103 |
35043 |
265 |
0 |
0 |
T118 |
5611 |
12 |
0 |
0 |
T120 |
180533 |
460 |
0 |
0 |
T125 |
68708 |
340 |
0 |
0 |
T126 |
7154 |
2 |
0 |
0 |
T145 |
4101 |
43 |
0 |
0 |
T155 |
39006 |
292 |
0 |
0 |
T156 |
9827 |
37 |
0 |
0 |
T157 |
66546 |
657 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
4720 |
0 |
0 |
T99 |
15490 |
165 |
0 |
0 |
T103 |
35043 |
194 |
0 |
0 |
T118 |
5611 |
6 |
0 |
0 |
T120 |
180533 |
439 |
0 |
0 |
T125 |
68708 |
317 |
0 |
0 |
T126 |
7154 |
119 |
0 |
0 |
T145 |
4101 |
55 |
0 |
0 |
T155 |
39006 |
279 |
0 |
0 |
T156 |
9827 |
44 |
0 |
0 |
T157 |
66546 |
780 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
4484 |
0 |
0 |
T99 |
15490 |
126 |
0 |
0 |
T103 |
35043 |
292 |
0 |
0 |
T118 |
5611 |
67 |
0 |
0 |
T120 |
180533 |
445 |
0 |
0 |
T125 |
68708 |
342 |
0 |
0 |
T126 |
7154 |
67 |
0 |
0 |
T145 |
4101 |
53 |
0 |
0 |
T155 |
39006 |
258 |
0 |
0 |
T156 |
9827 |
28 |
0 |
0 |
T157 |
66546 |
383 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
4262 |
0 |
0 |
T99 |
15490 |
171 |
0 |
0 |
T103 |
35043 |
234 |
0 |
0 |
T118 |
5611 |
51 |
0 |
0 |
T120 |
180533 |
446 |
0 |
0 |
T125 |
68708 |
301 |
0 |
0 |
T126 |
7154 |
60 |
0 |
0 |
T145 |
4101 |
39 |
0 |
0 |
T155 |
39006 |
268 |
0 |
0 |
T156 |
9827 |
8 |
0 |
0 |
T157 |
66546 |
377 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
4394 |
0 |
0 |
T99 |
15490 |
61 |
0 |
0 |
T103 |
35043 |
249 |
0 |
0 |
T105 |
11501 |
5 |
0 |
0 |
T120 |
180533 |
473 |
0 |
0 |
T125 |
68708 |
330 |
0 |
0 |
T126 |
7154 |
80 |
0 |
0 |
T155 |
39006 |
299 |
0 |
0 |
T156 |
9827 |
75 |
0 |
0 |
T157 |
66546 |
523 |
0 |
0 |
T158 |
14646 |
11 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
4079 |
0 |
0 |
T99 |
15490 |
44 |
0 |
0 |
T103 |
35043 |
327 |
0 |
0 |
T118 |
5611 |
48 |
0 |
0 |
T120 |
180533 |
490 |
0 |
0 |
T125 |
68708 |
292 |
0 |
0 |
T126 |
7154 |
4 |
0 |
0 |
T145 |
4101 |
55 |
0 |
0 |
T155 |
39006 |
269 |
0 |
0 |
T156 |
9827 |
10 |
0 |
0 |
T157 |
66546 |
400 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
4178 |
0 |
0 |
T99 |
15490 |
62 |
0 |
0 |
T103 |
35043 |
220 |
0 |
0 |
T118 |
5611 |
46 |
0 |
0 |
T120 |
180533 |
447 |
0 |
0 |
T125 |
68708 |
322 |
0 |
0 |
T126 |
7154 |
64 |
0 |
0 |
T145 |
4101 |
42 |
0 |
0 |
T155 |
39006 |
241 |
0 |
0 |
T156 |
9827 |
50 |
0 |
0 |
T157 |
66546 |
527 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
4163 |
0 |
0 |
T99 |
15490 |
178 |
0 |
0 |
T101 |
21071 |
5 |
0 |
0 |
T103 |
35043 |
124 |
0 |
0 |
T118 |
5611 |
49 |
0 |
0 |
T120 |
180533 |
449 |
0 |
0 |
T125 |
68708 |
335 |
0 |
0 |
T126 |
7154 |
111 |
0 |
0 |
T145 |
4101 |
2 |
0 |
0 |
T155 |
39006 |
257 |
0 |
0 |
T156 |
9827 |
30 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
4115 |
0 |
0 |
T99 |
15490 |
56 |
0 |
0 |
T103 |
35043 |
307 |
0 |
0 |
T118 |
5611 |
52 |
0 |
0 |
T120 |
180533 |
387 |
0 |
0 |
T125 |
68708 |
247 |
0 |
0 |
T126 |
7154 |
92 |
0 |
0 |
T145 |
4101 |
8 |
0 |
0 |
T155 |
39006 |
242 |
0 |
0 |
T156 |
9827 |
21 |
0 |
0 |
T157 |
66546 |
529 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
4442 |
0 |
0 |
T99 |
15490 |
111 |
0 |
0 |
T103 |
35043 |
262 |
0 |
0 |
T118 |
5611 |
7 |
0 |
0 |
T120 |
180533 |
427 |
0 |
0 |
T125 |
68708 |
280 |
0 |
0 |
T126 |
7154 |
13 |
0 |
0 |
T155 |
39006 |
290 |
0 |
0 |
T156 |
9827 |
34 |
0 |
0 |
T157 |
66546 |
613 |
0 |
0 |
T158 |
14646 |
89 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
4077 |
0 |
0 |
T99 |
15490 |
130 |
0 |
0 |
T103 |
35043 |
217 |
0 |
0 |
T118 |
5611 |
41 |
0 |
0 |
T120 |
180533 |
440 |
0 |
0 |
T125 |
68708 |
278 |
0 |
0 |
T126 |
7154 |
53 |
0 |
0 |
T145 |
4101 |
51 |
0 |
0 |
T155 |
39006 |
265 |
0 |
0 |
T156 |
9827 |
62 |
0 |
0 |
T157 |
66546 |
510 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
4112 |
0 |
0 |
T99 |
15490 |
121 |
0 |
0 |
T103 |
35043 |
317 |
0 |
0 |
T118 |
5611 |
7 |
0 |
0 |
T120 |
180533 |
395 |
0 |
0 |
T125 |
68708 |
281 |
0 |
0 |
T126 |
7154 |
68 |
0 |
0 |
T145 |
4101 |
56 |
0 |
0 |
T155 |
39006 |
296 |
0 |
0 |
T156 |
9827 |
37 |
0 |
0 |
T157 |
66546 |
537 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
4227 |
0 |
0 |
T99 |
15490 |
141 |
0 |
0 |
T103 |
35043 |
124 |
0 |
0 |
T118 |
5611 |
7 |
0 |
0 |
T120 |
180533 |
422 |
0 |
0 |
T125 |
68708 |
270 |
0 |
0 |
T126 |
7154 |
58 |
0 |
0 |
T145 |
4101 |
31 |
0 |
0 |
T155 |
39006 |
235 |
0 |
0 |
T156 |
9827 |
11 |
0 |
0 |
T157 |
66546 |
478 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
4182 |
0 |
0 |
T99 |
15490 |
85 |
0 |
0 |
T103 |
35043 |
253 |
0 |
0 |
T118 |
5611 |
47 |
0 |
0 |
T120 |
180533 |
477 |
0 |
0 |
T125 |
68708 |
263 |
0 |
0 |
T126 |
7154 |
120 |
0 |
0 |
T145 |
4101 |
5 |
0 |
0 |
T155 |
39006 |
258 |
0 |
0 |
T156 |
9827 |
65 |
0 |
0 |
T157 |
66546 |
602 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
4521 |
0 |
0 |
T99 |
15490 |
95 |
0 |
0 |
T103 |
35043 |
221 |
0 |
0 |
T118 |
5611 |
55 |
0 |
0 |
T120 |
180533 |
379 |
0 |
0 |
T125 |
68708 |
330 |
0 |
0 |
T126 |
7154 |
12 |
0 |
0 |
T155 |
39006 |
287 |
0 |
0 |
T156 |
9827 |
19 |
0 |
0 |
T157 |
66546 |
662 |
0 |
0 |
T158 |
14646 |
31 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
4404 |
0 |
0 |
T99 |
15490 |
54 |
0 |
0 |
T103 |
35043 |
211 |
0 |
0 |
T118 |
5611 |
38 |
0 |
0 |
T120 |
180533 |
448 |
0 |
0 |
T125 |
68708 |
281 |
0 |
0 |
T126 |
7154 |
65 |
0 |
0 |
T145 |
4101 |
67 |
0 |
0 |
T155 |
39006 |
272 |
0 |
0 |
T156 |
9827 |
57 |
0 |
0 |
T157 |
66546 |
551 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
4611 |
0 |
0 |
T99 |
15490 |
68 |
0 |
0 |
T103 |
35043 |
269 |
0 |
0 |
T118 |
5611 |
70 |
0 |
0 |
T120 |
180533 |
493 |
0 |
0 |
T125 |
68708 |
276 |
0 |
0 |
T126 |
7154 |
40 |
0 |
0 |
T145 |
4101 |
1 |
0 |
0 |
T155 |
39006 |
259 |
0 |
0 |
T156 |
9827 |
35 |
0 |
0 |
T157 |
66546 |
491 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
2255 |
0 |
0 |
T99 |
15490 |
20 |
0 |
0 |
T103 |
35043 |
62 |
0 |
0 |
T118 |
5611 |
5 |
0 |
0 |
T120 |
180533 |
421 |
0 |
0 |
T125 |
68708 |
301 |
0 |
0 |
T126 |
7154 |
13 |
0 |
0 |
T145 |
4101 |
6 |
0 |
0 |
T155 |
39006 |
244 |
0 |
0 |
T156 |
9827 |
8 |
0 |
0 |
T157 |
66546 |
107 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
2401 |
0 |
0 |
T99 |
15490 |
37 |
0 |
0 |
T103 |
35043 |
57 |
0 |
0 |
T118 |
5611 |
9 |
0 |
0 |
T120 |
180533 |
448 |
0 |
0 |
T125 |
68708 |
336 |
0 |
0 |
T126 |
7154 |
18 |
0 |
0 |
T145 |
4101 |
1 |
0 |
0 |
T155 |
39006 |
265 |
0 |
0 |
T156 |
9827 |
14 |
0 |
0 |
T157 |
66546 |
107 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
2300 |
0 |
0 |
T99 |
15490 |
46 |
0 |
0 |
T103 |
35043 |
63 |
0 |
0 |
T118 |
5611 |
6 |
0 |
0 |
T120 |
180533 |
393 |
0 |
0 |
T125 |
68708 |
271 |
0 |
0 |
T126 |
7154 |
10 |
0 |
0 |
T145 |
4101 |
10 |
0 |
0 |
T155 |
39006 |
287 |
0 |
0 |
T156 |
9827 |
17 |
0 |
0 |
T157 |
66546 |
80 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
2233 |
0 |
0 |
T99 |
15490 |
25 |
0 |
0 |
T103 |
35043 |
48 |
0 |
0 |
T118 |
5611 |
15 |
0 |
0 |
T120 |
180533 |
459 |
0 |
0 |
T125 |
68708 |
232 |
0 |
0 |
T126 |
7154 |
9 |
0 |
0 |
T155 |
39006 |
261 |
0 |
0 |
T156 |
9827 |
11 |
0 |
0 |
T157 |
66546 |
127 |
0 |
0 |
T158 |
14646 |
5 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
2669 |
0 |
0 |
T99 |
15490 |
32 |
0 |
0 |
T103 |
35043 |
98 |
0 |
0 |
T118 |
5611 |
10 |
0 |
0 |
T120 |
180533 |
403 |
0 |
0 |
T125 |
68708 |
257 |
0 |
0 |
T126 |
7154 |
21 |
0 |
0 |
T145 |
4101 |
4 |
0 |
0 |
T155 |
39006 |
258 |
0 |
0 |
T156 |
9827 |
23 |
0 |
0 |
T157 |
66546 |
167 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
3817 |
0 |
0 |
T8 |
322422 |
22 |
0 |
0 |
T9 |
25463 |
0 |
0 |
0 |
T10 |
11528 |
0 |
0 |
0 |
T11 |
6928 |
0 |
0 |
0 |
T12 |
1263 |
0 |
0 |
0 |
T13 |
158817 |
0 |
0 |
0 |
T14 |
110568 |
0 |
0 |
0 |
T23 |
3367 |
0 |
0 |
0 |
T24 |
692 |
0 |
0 |
0 |
T25 |
1555 |
0 |
0 |
0 |
T35 |
0 |
8 |
0 |
0 |
T143 |
0 |
7 |
0 |
0 |
T144 |
0 |
8 |
0 |
0 |
T159 |
0 |
30 |
0 |
0 |
T160 |
0 |
10 |
0 |
0 |
T161 |
0 |
34 |
0 |
0 |
T162 |
0 |
61 |
0 |
0 |
T163 |
0 |
13 |
0 |
0 |
T164 |
0 |
20 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
2355 |
0 |
0 |
T99 |
15490 |
20 |
0 |
0 |
T103 |
35043 |
73 |
0 |
0 |
T118 |
5611 |
15 |
0 |
0 |
T120 |
180533 |
455 |
0 |
0 |
T125 |
68708 |
251 |
0 |
0 |
T126 |
7154 |
11 |
0 |
0 |
T145 |
4101 |
2 |
0 |
0 |
T155 |
39006 |
288 |
0 |
0 |
T156 |
9827 |
11 |
0 |
0 |
T157 |
66546 |
115 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
2370 |
0 |
0 |
T99 |
15490 |
25 |
0 |
0 |
T103 |
35043 |
28 |
0 |
0 |
T118 |
5611 |
12 |
0 |
0 |
T120 |
180533 |
430 |
0 |
0 |
T125 |
68708 |
279 |
0 |
0 |
T126 |
7154 |
9 |
0 |
0 |
T145 |
4101 |
4 |
0 |
0 |
T155 |
39006 |
279 |
0 |
0 |
T156 |
9827 |
6 |
0 |
0 |
T157 |
66546 |
130 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
2244 |
0 |
0 |
T99 |
15490 |
24 |
0 |
0 |
T103 |
35043 |
29 |
0 |
0 |
T118 |
5611 |
8 |
0 |
0 |
T120 |
180533 |
448 |
0 |
0 |
T125 |
68708 |
271 |
0 |
0 |
T126 |
7154 |
16 |
0 |
0 |
T145 |
4101 |
2 |
0 |
0 |
T155 |
39006 |
256 |
0 |
0 |
T156 |
9827 |
2 |
0 |
0 |
T157 |
66546 |
82 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
2184 |
0 |
0 |
T99 |
15490 |
22 |
0 |
0 |
T103 |
35043 |
46 |
0 |
0 |
T118 |
5611 |
6 |
0 |
0 |
T120 |
180533 |
438 |
0 |
0 |
T125 |
68708 |
249 |
0 |
0 |
T126 |
7154 |
5 |
0 |
0 |
T145 |
4101 |
6 |
0 |
0 |
T155 |
39006 |
282 |
0 |
0 |
T156 |
9827 |
7 |
0 |
0 |
T157 |
66546 |
77 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
2169 |
0 |
0 |
T99 |
15490 |
17 |
0 |
0 |
T103 |
35043 |
39 |
0 |
0 |
T118 |
5611 |
1 |
0 |
0 |
T120 |
180533 |
420 |
0 |
0 |
T125 |
68708 |
312 |
0 |
0 |
T126 |
7154 |
11 |
0 |
0 |
T145 |
4101 |
9 |
0 |
0 |
T155 |
39006 |
288 |
0 |
0 |
T156 |
9827 |
9 |
0 |
0 |
T157 |
66546 |
76 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
2257 |
0 |
0 |
T99 |
15490 |
26 |
0 |
0 |
T103 |
35043 |
39 |
0 |
0 |
T118 |
5611 |
14 |
0 |
0 |
T120 |
180533 |
444 |
0 |
0 |
T125 |
68708 |
285 |
0 |
0 |
T126 |
7154 |
7 |
0 |
0 |
T145 |
4101 |
7 |
0 |
0 |
T155 |
39006 |
287 |
0 |
0 |
T156 |
9827 |
5 |
0 |
0 |
T157 |
66546 |
85 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
2659 |
0 |
0 |
T99 |
15490 |
43 |
0 |
0 |
T103 |
35043 |
121 |
0 |
0 |
T118 |
5611 |
22 |
0 |
0 |
T120 |
180533 |
408 |
0 |
0 |
T125 |
68708 |
300 |
0 |
0 |
T126 |
7154 |
26 |
0 |
0 |
T145 |
4101 |
27 |
0 |
0 |
T155 |
39006 |
218 |
0 |
0 |
T156 |
9827 |
21 |
0 |
0 |
T157 |
66546 |
265 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
2246 |
0 |
0 |
T99 |
15490 |
16 |
0 |
0 |
T103 |
35043 |
39 |
0 |
0 |
T118 |
5611 |
12 |
0 |
0 |
T120 |
180533 |
419 |
0 |
0 |
T125 |
68708 |
249 |
0 |
0 |
T126 |
7154 |
7 |
0 |
0 |
T145 |
4101 |
3 |
0 |
0 |
T155 |
39006 |
311 |
0 |
0 |
T156 |
9827 |
6 |
0 |
0 |
T157 |
66546 |
85 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
3063 |
0 |
0 |
T99 |
15490 |
24 |
0 |
0 |
T103 |
35043 |
135 |
0 |
0 |
T118 |
5611 |
17 |
0 |
0 |
T120 |
180533 |
502 |
0 |
0 |
T125 |
68708 |
312 |
0 |
0 |
T126 |
7154 |
24 |
0 |
0 |
T145 |
4101 |
23 |
0 |
0 |
T155 |
39006 |
289 |
0 |
0 |
T156 |
9827 |
26 |
0 |
0 |
T157 |
66546 |
200 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
2293 |
0 |
0 |
T99 |
15490 |
31 |
0 |
0 |
T103 |
35043 |
50 |
0 |
0 |
T118 |
5611 |
2 |
0 |
0 |
T120 |
180533 |
401 |
0 |
0 |
T125 |
68708 |
222 |
0 |
0 |
T126 |
7154 |
5 |
0 |
0 |
T145 |
4101 |
11 |
0 |
0 |
T155 |
39006 |
276 |
0 |
0 |
T156 |
9827 |
16 |
0 |
0 |
T157 |
66546 |
113 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
2159 |
0 |
0 |
T99 |
15490 |
29 |
0 |
0 |
T103 |
35043 |
21 |
0 |
0 |
T118 |
5611 |
4 |
0 |
0 |
T120 |
180533 |
440 |
0 |
0 |
T125 |
68708 |
308 |
0 |
0 |
T126 |
7154 |
5 |
0 |
0 |
T145 |
4101 |
1 |
0 |
0 |
T155 |
39006 |
274 |
0 |
0 |
T156 |
9827 |
6 |
0 |
0 |
T157 |
66546 |
66 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
2360 |
0 |
0 |
T99 |
15490 |
12 |
0 |
0 |
T103 |
35043 |
28 |
0 |
0 |
T118 |
5611 |
7 |
0 |
0 |
T120 |
180533 |
454 |
0 |
0 |
T125 |
68708 |
345 |
0 |
0 |
T126 |
7154 |
5 |
0 |
0 |
T145 |
4101 |
6 |
0 |
0 |
T155 |
39006 |
278 |
0 |
0 |
T156 |
9827 |
21 |
0 |
0 |
T157 |
66546 |
95 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
2260 |
0 |
0 |
T99 |
15490 |
25 |
0 |
0 |
T103 |
35043 |
34 |
0 |
0 |
T118 |
5611 |
12 |
0 |
0 |
T120 |
180533 |
428 |
0 |
0 |
T125 |
68708 |
267 |
0 |
0 |
T126 |
7154 |
1 |
0 |
0 |
T145 |
4101 |
7 |
0 |
0 |
T155 |
39006 |
268 |
0 |
0 |
T156 |
9827 |
6 |
0 |
0 |
T157 |
66546 |
104 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
2227 |
0 |
0 |
T99 |
15490 |
23 |
0 |
0 |
T103 |
35043 |
36 |
0 |
0 |
T118 |
5611 |
12 |
0 |
0 |
T120 |
180533 |
470 |
0 |
0 |
T125 |
68708 |
260 |
0 |
0 |
T126 |
7154 |
9 |
0 |
0 |
T145 |
4101 |
6 |
0 |
0 |
T155 |
39006 |
258 |
0 |
0 |
T157 |
66546 |
70 |
0 |
0 |
T158 |
14646 |
21 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
2141 |
0 |
0 |
T99 |
15490 |
17 |
0 |
0 |
T103 |
35043 |
40 |
0 |
0 |
T118 |
5611 |
10 |
0 |
0 |
T120 |
180533 |
442 |
0 |
0 |
T125 |
68708 |
345 |
0 |
0 |
T126 |
7154 |
7 |
0 |
0 |
T145 |
4101 |
3 |
0 |
0 |
T155 |
39006 |
242 |
0 |
0 |
T156 |
9827 |
8 |
0 |
0 |
T157 |
66546 |
61 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
505151376 |
2176 |
0 |
0 |
T99 |
15490 |
24 |
0 |
0 |
T103 |
35043 |
45 |
0 |
0 |
T118 |
5611 |
12 |
0 |
0 |
T120 |
180533 |
393 |
0 |
0 |
T125 |
68708 |
336 |
0 |
0 |
T126 |
7154 |
5 |
0 |
0 |
T145 |
4101 |
4 |
0 |
0 |
T155 |
39006 |
294 |
0 |
0 |
T156 |
9827 |
13 |
0 |
0 |
T157 |
66546 |
74 |
0 |
0 |