Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3264723	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4071823

1

T1

3

T2

11977

T3

2306

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4002083	1			T1	1		T2	2545		T3	2776
values[0x0]	1665782	1			T1	3		T2	5324		T3	472
values[0x1]	1668681	1			T1	11		T2	5253		T3	445

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2323946	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5012600

1

T1

3

T2

12242

T3

2601

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27696	1			T4	82		T6	4		T7	170
valid_sources[0x01]	29633	1			T4	54		T7	65		T12	279
valid_sources[0x02]	25622	1			T4	60		T6	10		T7	281
valid_sources[0x03]	27163	1			T4	85		T6	3		T7	864
valid_sources[0x04]	27038	1			T2	832		T4	78		T6	3
valid_sources[0x05]	36552	1			T2	1		T4	90		T6	1
valid_sources[0x06]	30247	1			T4	82		T7	14		T9	5
valid_sources[0x07]	28070	1			T4	73		T6	5		T7	63
valid_sources[0x08]	30685	1			T4	64		T7	92		T9	5
valid_sources[0x09]	28075	1			T4	89		T6	1		T7	46
valid_sources[0x0a]	30941	1			T4	72		T6	1		T7	51
valid_sources[0x0b]	25337	1			T4	55		T6	10		T9	6
valid_sources[0x0c]	31100	1			T4	57		T7	297		T9	6
valid_sources[0x0d]	29481	1			T2	89		T4	80		T7	88
valid_sources[0x0e]	26505	1			T4	57		T6	4		T7	44
valid_sources[0x0f]	26872	1			T4	83		T6	7		T7	133
valid_sources[0x10]	34184	1			T1	1		T4	73		T6	2
valid_sources[0x11]	28746	1			T4	86		T6	4		T7	1
valid_sources[0x12]	25805	1			T4	64		T6	7		T7	331
valid_sources[0x13]	27348	1			T4	67		T6	6		T7	425
valid_sources[0x14]	28223	1			T2	416		T4	50		T6	7
valid_sources[0x15]	27616	1			T4	75		T7	1		T9	11
valid_sources[0x16]	27675	1			T4	48		T6	15		T7	24
valid_sources[0x17]	31364	1			T2	1		T4	65		T7	147
valid_sources[0x18]	27161	1			T4	83		T7	1		T9	7
valid_sources[0x19]	27737	1			T2	1719		T4	72		T5	2
valid_sources[0x1a]	28412	1			T4	86		T7	29		T9	5
valid_sources[0x1b]	28788	1			T4	62		T6	3		T7	292
valid_sources[0x1c]	58460	1			T4	60		T6	2		T7	168
valid_sources[0x1d]	26507	1			T4	54		T6	5		T7	739
valid_sources[0x1e]	24757	1			T4	55		T6	1		T9	1
valid_sources[0x1f]	28296	1			T4	71		T6	1		T7	6
valid_sources[0x20]	29777	1			T4	62		T6	3		T9	6
valid_sources[0x21]	28022	1			T4	52		T5	1		T7	51
valid_sources[0x22]	25504	1			T4	69		T6	4		T7	69
valid_sources[0x23]	27831	1			T4	56		T6	9		T7	127
valid_sources[0x24]	26396	1			T4	79		T5	2		T6	4
valid_sources[0x25]	28726	1			T2	2		T4	86		T7	1
valid_sources[0x26]	29535	1			T2	2		T4	64		T6	1
valid_sources[0x27]	26091	1			T4	65		T6	1		T7	113
valid_sources[0x28]	25310	1			T2	1		T4	79		T9	2
valid_sources[0x29]	26992	1			T4	50		T6	6		T7	97
valid_sources[0x2a]	27282	1			T4	81		T6	4		T7	238
valid_sources[0x2b]	26545	1			T4	93		T6	8		T7	153
valid_sources[0x2c]	25903	1			T2	506		T4	84		T6	4
valid_sources[0x2d]	25980	1			T4	81		T6	4		T7	30
valid_sources[0x2e]	26816	1			T1	4		T4	74		T7	57
valid_sources[0x2f]	28183	1			T4	73		T6	1		T7	69
valid_sources[0x30]	27794	1			T3	718		T4	52		T5	1
valid_sources[0x31]	31663	1			T4	100		T6	6		T7	103
valid_sources[0x32]	26550	1			T4	77		T7	172		T13	10
valid_sources[0x33]	28683	1			T2	2		T4	60		T6	5
valid_sources[0x34]	29687	1			T2	1		T4	72		T6	16
valid_sources[0x35]	28148	1			T2	1		T4	59		T7	145
valid_sources[0x36]	29795	1			T4	58		T7	64		T9	4
valid_sources[0x37]	25922	1			T4	64		T6	2		T7	28
valid_sources[0x38]	26292	1			T4	94		T7	166		T9	9
valid_sources[0x39]	27203	1			T4	62		T7	2		T9	6
valid_sources[0x3a]	27123	1			T4	81		T6	2		T7	406
valid_sources[0x3b]	26843	1			T4	75		T7	1		T9	10
valid_sources[0x3c]	25889	1			T4	49		T7	88		T9	7
valid_sources[0x3d]	28324	1			T4	58		T6	11		T7	19
valid_sources[0x3e]	25135	1			T4	72		T6	4		T7	1
valid_sources[0x3f]	30405	1			T4	62		T7	3		T9	2
valid_sources[0x40]	27003	1			T1	2		T4	58		T7	75
valid_sources[0x41]	32973	1			T4	66		T6	2		T7	48
valid_sources[0x42]	26831	1			T4	74		T6	1		T7	186
valid_sources[0x43]	24751	1			T4	58		T6	2		T7	112
valid_sources[0x44]	27990	1			T2	761		T4	63		T6	5
valid_sources[0x45]	27216	1			T4	77		T6	2		T7	151
valid_sources[0x46]	25264	1			T4	94		T7	309		T9	4
valid_sources[0x47]	30606	1			T2	1		T4	65		T6	11
valid_sources[0x48]	28051	1			T4	56		T6	2		T7	153
valid_sources[0x49]	28623	1			T2	1		T4	83		T6	11
valid_sources[0x4a]	26156	1			T4	78		T6	2		T7	10
valid_sources[0x4b]	29602	1			T4	52		T6	3		T7	20
valid_sources[0x4c]	28278	1			T4	66		T6	1		T7	59
valid_sources[0x4d]	30518	1			T4	81		T6	25		T7	7
valid_sources[0x4e]	28160	1			T4	75		T6	14		T7	273
valid_sources[0x4f]	25181	1			T4	87		T6	1		T7	1
valid_sources[0x50]	27099	1			T2	1		T4	51		T7	52
valid_sources[0x51]	25407	1			T2	2		T4	52		T6	4
valid_sources[0x52]	60404	1			T4	77		T6	9		T7	2
valid_sources[0x53]	25271	1			T4	79		T6	4		T7	16
valid_sources[0x54]	27804	1			T4	76		T6	7		T7	138
valid_sources[0x55]	28471	1			T4	51		T5	1		T6	2
valid_sources[0x56]	26626	1			T4	65		T6	3		T7	86
valid_sources[0x57]	29269	1			T4	77		T7	507		T9	2
valid_sources[0x58]	26425	1			T4	81		T7	26		T9	4
valid_sources[0x59]	24739	1			T4	69		T6	6		T7	33
valid_sources[0x5a]	26703	1			T4	62		T7	205		T13	5
valid_sources[0x5b]	26220	1			T4	55		T7	14		T9	7
valid_sources[0x5c]	26277	1			T4	82		T5	1		T6	5
valid_sources[0x5d]	28920	1			T2	1		T4	59		T7	109
valid_sources[0x5e]	28816	1			T4	49		T6	2		T7	152
valid_sources[0x5f]	37327	1			T4	79		T7	162		T9	7
valid_sources[0x60]	30973	1			T4	64		T6	5		T7	29
valid_sources[0x61]	27597	1			T2	2		T4	55		T6	6
valid_sources[0x62]	27674	1			T4	55		T6	1		T7	147
valid_sources[0x63]	29992	1			T2	1		T4	63		T7	7
valid_sources[0x64]	28204	1			T4	68		T7	66		T9	7
valid_sources[0x65]	28152	1			T4	60		T7	44		T9	3
valid_sources[0x66]	24572	1			T4	76		T6	11		T7	140
valid_sources[0x67]	25195	1			T2	1		T4	81		T6	1
valid_sources[0x68]	29695	1			T4	72		T7	207		T9	6
valid_sources[0x69]	25404	1			T4	73		T7	19		T9	4
valid_sources[0x6a]	29942	1			T4	72		T6	3		T9	13
valid_sources[0x6b]	26720	1			T4	63		T6	5		T7	13
valid_sources[0x6c]	28328	1			T2	1		T4	71		T6	5
valid_sources[0x6d]	28143	1			T4	72		T6	2		T7	24
valid_sources[0x6e]	26213	1			T2	1		T4	63		T6	11
valid_sources[0x6f]	28924	1			T4	67		T7	53		T9	8
valid_sources[0x70]	27984	1			T4	73		T6	2		T7	143
valid_sources[0x71]	26923	1			T4	66		T6	4		T7	188
valid_sources[0x72]	36505	1			T2	1		T4	71		T7	62
valid_sources[0x73]	28386	1			T4	66		T7	158		T9	3
valid_sources[0x74]	28464	1			T4	74		T6	3		T7	6
valid_sources[0x75]	27435	1			T4	59		T6	8		T7	324
valid_sources[0x76]	30963	1			T4	61		T7	109		T9	4
valid_sources[0x77]	30015	1			T4	75		T7	156		T9	9
valid_sources[0x78]	26007	1			T4	83		T6	4		T7	397
valid_sources[0x79]	40204	1			T2	1		T4	60		T6	1
valid_sources[0x7a]	25738	1			T4	56		T7	296		T9	8
valid_sources[0x7b]	28377	1			T4	81		T6	3		T7	178
valid_sources[0x7c]	23893	1			T1	1		T4	68		T6	6
valid_sources[0x7d]	26718	1			T4	60		T6	4		T9	7
valid_sources[0x7e]	27638	1			T4	76		T6	5		T7	64
valid_sources[0x7f]	27610	1			T4	76		T6	4		T7	209
valid_sources[0x80]	29314	1			T4	83		T7	450		T9	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1031849

1

T2

1457

T3

1394

T4

1436

values[0x0]

all_enables

biggest_size

1529614

1

T1

1

T2

5305

T3

470

values[0x1]

all_enables

biggest_size

1510360

1

T1

2

T2

5215

T3

442