Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3288503

1

T1

12

T2

1145

T3

1387

full_word

4071048

1

T1

3

T2

11977

T3

2306

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7359091	1			T1	15		T2	13122		T3	3693
auto[TlIntgErrCmd]	154	1			T99	10		T102	4		T103	10
auto[TlIntgErrData]	157	1			T99	9		T102	4		T103	9
auto[TlIntgErrBoth]	149	1			T99	11		T102	2		T103	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4006131

1

T1

1

T2

2545

T3

2776

auto[1]

3353420

1

T1

14

T2

10577

T3

917

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	2973848	1			T1	1		T2	1088		T3	1382
auto[TlIntgErrNone]	partial	auto[1]	314224	1			T1	11		T2	57		T3	5
auto[TlIntgErrNone]	full_word	auto[0]	1032060	1			T2	1457		T3	1394		T4	1436
auto[TlIntgErrNone]	full_word	auto[1]	3038959	1			T1	3		T2	10520		T3	912
auto[TlIntgErrCmd]	partial	auto[0]	65	1			T99	2		T103	4		T178	5
auto[TlIntgErrCmd]	partial	auto[1]	85	1			T99	8		T102	4		T103	6
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T178	1		T181	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T182	1		T181	1		-	-
auto[TlIntgErrData]	partial	auto[0]	77	1			T99	5		T102	2		T103	4
auto[TlIntgErrData]	partial	auto[1]	65	1			T99	4		T102	2		T103	5
auto[TlIntgErrData]	full_word	auto[0]	7	1			T182	1		T183	3		T179	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T178	2		T179	1		T176	1
auto[TlIntgErrBoth]	partial	auto[0]	68	1			T99	5		T102	1		T103	4
auto[TlIntgErrBoth]	partial	auto[1]	71	1			T99	3		T102	1		T103	7
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T99	1		T182	1		T184	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T99	2		T182	1		T181	1