Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	445940439	2819878	0	0
DepthKnown_A	445940439	445801871	0	0
RvalidKnown_A	445940439	445801871	0	0
WreadyKnown_A	445940439	445801871	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445940439	2819878	0	0
T2	116218	14152	0	0
T3	60800	832	0	0
T4	463266	9148	0	0
T5	898	0	0	0
T6	8513	832	0	0
T7	116183	5821	0	0
T8	3380	0	0	0
T9	26805	1663	0	0
T10	506849	0	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	1670	0	0
T14	0	1663	0	0
T24	1149	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445940439	445801871	0	0
T1	1087	1023	0	0
T2	116218	116212	0	0
T3	60800	60739	0	0
T4	463266	463169	0	0
T5	898	822	0	0
T6	8513	8413	0	0
T7	116183	116176	0	0
T8	3380	3133	0	0
T9	26805	26712	0	0
T10	506849	506778	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445940439	445801871	0	0
T1	1087	1023	0	0
T2	116218	116212	0	0
T3	60800	60739	0	0
T4	463266	463169	0	0
T5	898	822	0	0
T6	8513	8413	0	0
T7	116183	116176	0	0
T8	3380	3133	0	0
T9	26805	26712	0	0
T10	506849	506778	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445940439	445801871	0	0
T1	1087	1023	0	0
T2	116218	116212	0	0
T3	60800	60739	0	0
T4	463266	463169	0	0
T5	898	822	0	0
T6	8513	8413	0	0
T7	116183	116176	0	0
T8	3380	3133	0	0
T9	26805	26712	0	0
T10	506849	506778	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	445940439	3191728	0	0
DepthKnown_A	445940439	445801871	0	0
RvalidKnown_A	445940439	445801871	0	0
WreadyKnown_A	445940439	445801871	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445940439	3191728	0	0
T2	116218	30820	0	0
T3	60800	832	0	0
T4	463266	5824	0	0
T5	898	0	0	0
T6	8513	832	0	0
T7	116183	3328	0	0
T8	3380	0	0	0
T9	26805	832	0	0
T10	506849	0	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	839	0	0
T14	0	832	0	0
T24	1149	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445940439	445801871	0	0
T1	1087	1023	0	0
T2	116218	116212	0	0
T3	60800	60739	0	0
T4	463266	463169	0	0
T5	898	822	0	0
T6	8513	8413	0	0
T7	116183	116176	0	0
T8	3380	3133	0	0
T9	26805	26712	0	0
T10	506849	506778	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445940439	445801871	0	0
T1	1087	1023	0	0
T2	116218	116212	0	0
T3	60800	60739	0	0
T4	463266	463169	0	0
T5	898	822	0	0
T6	8513	8413	0	0
T7	116183	116176	0	0
T8	3380	3133	0	0
T9	26805	26712	0	0
T10	506849	506778	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445940439	445801871	0	0
T1	1087	1023	0	0
T2	116218	116212	0	0
T3	60800	60739	0	0
T4	463266	463169	0	0
T5	898	822	0	0
T6	8513	8413	0	0
T7	116183	116176	0	0
T8	3380	3133	0	0
T9	26805	26712	0	0
T10	506849	506778	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	445940439	182054	0	0
DepthKnown_A	445940439	445801871	0	0
RvalidKnown_A	445940439	445801871	0	0
WreadyKnown_A	445940439	445801871	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445940439	182054	0	0
T2	116218	481	0	0
T3	60800	0	0	0
T4	463266	958	0	0
T5	898	0	0	0
T6	8513	0	0	0
T7	116183	658	0	0
T8	3380	0	0	0
T9	26805	0	0	0
T10	506849	0	0	0
T11	0	128	0	0
T12	0	248	0	0
T24	1149	0	0	0
T26	0	138	0	0
T27	0	400	0	0
T28	0	903	0	0
T29	0	928	0	0
T30	0	460	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445940439	445801871	0	0
T1	1087	1023	0	0
T2	116218	116212	0	0
T3	60800	60739	0	0
T4	463266	463169	0	0
T5	898	822	0	0
T6	8513	8413	0	0
T7	116183	116176	0	0
T8	3380	3133	0	0
T9	26805	26712	0	0
T10	506849	506778	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445940439	445801871	0	0
T1	1087	1023	0	0
T2	116218	116212	0	0
T3	60800	60739	0	0
T4	463266	463169	0	0
T5	898	822	0	0
T6	8513	8413	0	0
T7	116183	116176	0	0
T8	3380	3133	0	0
T9	26805	26712	0	0
T10	506849	506778	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445940439	445801871	0	0
T1	1087	1023	0	0
T2	116218	116212	0	0
T3	60800	60739	0	0
T4	463266	463169	0	0
T5	898	822	0	0
T6	8513	8413	0	0
T7	116183	116176	0	0
T8	3380	3133	0	0
T9	26805	26712	0	0
T10	506849	506778	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	445940439	424776	0	0
DepthKnown_A	445940439	445801871	0	0
RvalidKnown_A	445940439	445801871	0	0
WreadyKnown_A	445940439	445801871	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445940439	424776	0	0
T2	116218	2112	0	0
T3	60800	0	0	0
T4	463266	958	0	0
T5	898	0	0	0
T6	8513	0	0	0
T7	116183	658	0	0
T8	3380	0	0	0
T9	26805	0	0	0
T10	506849	0	0	0
T11	0	128	0	0
T12	0	248	0	0
T24	1149	0	0	0
T26	0	138	0	0
T27	0	400	0	0
T28	0	3960	0	0
T29	0	4243	0	0
T30	0	2066	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445940439	445801871	0	0
T1	1087	1023	0	0
T2	116218	116212	0	0
T3	60800	60739	0	0
T4	463266	463169	0	0
T5	898	822	0	0
T6	8513	8413	0	0
T7	116183	116176	0	0
T8	3380	3133	0	0
T9	26805	26712	0	0
T10	506849	506778	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445940439	445801871	0	0
T1	1087	1023	0	0
T2	116218	116212	0	0
T3	60800	60739	0	0
T4	463266	463169	0	0
T5	898	822	0	0
T6	8513	8413	0	0
T7	116183	116176	0	0
T8	3380	3133	0	0
T9	26805	26712	0	0
T10	506849	506778	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445940439	445801871	0	0
T1	1087	1023	0	0
T2	116218	116212	0	0
T3	60800	60739	0	0
T4	463266	463169	0	0
T5	898	822	0	0
T6	8513	8413	0	0
T7	116183	116176	0	0
T8	3380	3133	0	0
T9	26805	26712	0	0
T10	506849	506778	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	445940439	5712490	0	0
DepthKnown_A	445940439	445801871	0	0
RvalidKnown_A	445940439	445801871	0	0
WreadyKnown_A	445940439	445801871	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445940439	5712490	0	0
T1	1087	15	0	0
T2	116218	2691	0	0
T3	60800	2862	0	0
T4	463266	10945	0	0
T5	898	15	0	0
T6	8513	58	0	0
T7	116183	22726	0	0
T8	3380	126	0	0
T9	26805	652	0	0
T10	506849	880	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445940439	445801871	0	0
T1	1087	1023	0	0
T2	116218	116212	0	0
T3	60800	60739	0	0
T4	463266	463169	0	0
T5	898	822	0	0
T6	8513	8413	0	0
T7	116183	116176	0	0
T8	3380	3133	0	0
T9	26805	26712	0	0
T10	506849	506778	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445940439	445801871	0	0
T1	1087	1023	0	0
T2	116218	116212	0	0
T3	60800	60739	0	0
T4	463266	463169	0	0
T5	898	822	0	0
T6	8513	8413	0	0
T7	116183	116176	0	0
T8	3380	3133	0	0
T9	26805	26712	0	0
T10	506849	506778	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445940439	445801871	0	0
T1	1087	1023	0	0
T2	116218	116212	0	0
T3	60800	60739	0	0
T4	463266	463169	0	0
T5	898	822	0	0
T6	8513	8413	0	0
T7	116183	116176	0	0
T8	3380	3133	0	0
T9	26805	26712	0	0
T10	506849	506778	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	445940439	12369930	0	0
DepthKnown_A	445940439	445801871	0	0
RvalidKnown_A	445940439	445801871	0	0
WreadyKnown_A	445940439	445801871	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445940439	12369930	0	0
T1	1087	15	0	0
T2	116218	11627	0	0
T3	60800	2861	0	0
T4	463266	10795	0	0
T5	898	67	0	0
T6	8513	58	0	0
T7	116183	22582	0	0
T8	3380	126	0	0
T9	26805	651	0	0
T10	506849	880	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445940439	445801871	0	0
T1	1087	1023	0	0
T2	116218	116212	0	0
T3	60800	60739	0	0
T4	463266	463169	0	0
T5	898	822	0	0
T6	8513	8413	0	0
T7	116183	116176	0	0
T8	3380	3133	0	0
T9	26805	26712	0	0
T10	506849	506778	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445940439	445801871	0	0
T1	1087	1023	0	0
T2	116218	116212	0	0
T3	60800	60739	0	0
T4	463266	463169	0	0
T5	898	822	0	0
T6	8513	8413	0	0
T7	116183	116176	0	0
T8	3380	3133	0	0
T9	26805	26712	0	0
T10	506849	506778	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445940439	445801871	0	0
T1	1087	1023	0	0
T2	116218	116212	0	0
T3	60800	60739	0	0
T4	463266	463169	0	0
T5	898	822	0	0
T6	8513	8413	0	0
T7	116183	116176	0	0
T8	3380	3133	0	0
T9	26805	26712	0	0
T10	506849	506778	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0