Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T12
1	0	Covered	T4,T7,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T10
1	0	Unreachable
1	1	Covered	T4,T7,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T7
1	0	Covered	T2,T4,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T2,T4,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T7
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	745897527	593214069	0	0
CheckNGreaterZero_A	2925	2925	0	0
GntImpliesReady_A	745897527	3668320	0	0
GntImpliesValid_A	745897527	3668320	0	0
GrantKnown_A	745897527	593214069	0	0
IdxKnown_A	745897527	593214069	0	0
IndexIsCorrect_A	745897527	3668320	0	0
LockArbDecision_A	745897527	0	0	0
NoReadyValidNoGrant_A	745897527	0	0	0
ReadyAndValidImplyGrant_A	745897527	3668320	0	0
ReqAndReadyImplyGrant_A	745897527	3668320	0	0
ReqImpliesValid_A	745897527	3668320	0	0
ReqStaysHighUntilGranted0_M	745897527	0	0	0
RoundRobin_A	745897527	5	0	975
ValidKnown_A	745897527	593214069	0	0
gen_data_port_assertion.DataFlow_A	745897527	3668320	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745897527	593214069	0	0
T1	1087	1023	0	0
T2	221595	221348	0	0
T3	112602	111887	0	0
T4	1321724	883619	0	0
T5	898	822	0	0
T6	8545	8429	0	0
T7	888249	497438	0	0
T8	3380	3133	0	0
T9	203387	114178	0	0
T10	666587	581786	0	0
T11	53376	26688	0	0
T12	196150	95755	0	0
T13	234586	116618	0	0
T14	0	192	0	0
T25	68212	64208	0	0
T26	59602	59104	0	0
T27	0	45872	0	0
T28	0	198336	0	0
T29	0	246448	0	0
T30	0	96272	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2925	2925	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745897527	3668320	0	0
T2	221595	18793	0	0
T3	112602	832	0	0
T4	1321724	15391	0	0
T5	898	0	0	0
T6	8545	832	0	0
T7	888249	9983	0	0
T8	3380	0	0	0
T9	203387	832	0	0
T10	666587	0	0	0
T11	53376	1992	0	0
T12	196150	3468	0	0
T13	234586	832	0	0
T24	1149	0	0	0
T25	68212	0	0	0
T26	59602	1102	0	0
T27	0	1987	0	0
T28	0	5033	0	0
T29	0	4798	0	0
T30	0	2465	0	0
T37	0	4961	0	0
T38	0	4274	0	0
T42	0	1663	0	0
T45	0	2	0	0
T47	0	1495	0	0
T52	0	2152	0	0
T53	0	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745897527	3668320	0	0
T2	221595	18793	0	0
T3	112602	832	0	0
T4	1321724	15391	0	0
T5	898	0	0	0
T6	8545	832	0	0
T7	888249	9983	0	0
T8	3380	0	0	0
T9	203387	832	0	0
T10	666587	0	0	0
T11	53376	1992	0	0
T12	196150	3468	0	0
T13	234586	832	0	0
T24	1149	0	0	0
T25	68212	0	0	0
T26	59602	1102	0	0
T27	0	1987	0	0
T28	0	5033	0	0
T29	0	4798	0	0
T30	0	2465	0	0
T37	0	4961	0	0
T38	0	4274	0	0
T42	0	1663	0	0
T45	0	2	0	0
T47	0	1495	0	0
T52	0	2152	0	0
T53	0	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745897527	593214069	0	0
T1	1087	1023	0	0
T2	221595	221348	0	0
T3	112602	111887	0	0
T4	1321724	883619	0	0
T5	898	822	0	0
T6	8545	8429	0	0
T7	888249	497438	0	0
T8	3380	3133	0	0
T9	203387	114178	0	0
T10	666587	581786	0	0
T11	53376	26688	0	0
T12	196150	95755	0	0
T13	234586	116618	0	0
T14	0	192	0	0
T25	68212	64208	0	0
T26	59602	59104	0	0
T27	0	45872	0	0
T28	0	198336	0	0
T29	0	246448	0	0
T30	0	96272	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745897527	593214069	0	0
T1	1087	1023	0	0
T2	221595	221348	0	0
T3	112602	111887	0	0
T4	1321724	883619	0	0
T5	898	822	0	0
T6	8545	8429	0	0
T7	888249	497438	0	0
T8	3380	3133	0	0
T9	203387	114178	0	0
T10	666587	581786	0	0
T11	53376	26688	0	0
T12	196150	95755	0	0
T13	234586	116618	0	0
T14	0	192	0	0
T25	68212	64208	0	0
T26	59602	59104	0	0
T27	0	45872	0	0
T28	0	198336	0	0
T29	0	246448	0	0
T30	0	96272	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745897527	3668320	0	0
T2	221595	18793	0	0
T3	112602	832	0	0
T4	1321724	15391	0	0
T5	898	0	0	0
T6	8545	832	0	0
T7	888249	9983	0	0
T8	3380	0	0	0
T9	203387	832	0	0
T10	666587	0	0	0
T11	53376	1992	0	0
T12	196150	3468	0	0
T13	234586	832	0	0
T24	1149	0	0	0
T25	68212	0	0	0
T26	59602	1102	0	0
T27	0	1987	0	0
T28	0	5033	0	0
T29	0	4798	0	0
T30	0	2465	0	0
T37	0	4961	0	0
T38	0	4274	0	0
T42	0	1663	0	0
T45	0	2	0	0
T47	0	1495	0	0
T52	0	2152	0	0
T53	0	4	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745897527	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745897527	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745897527	3668320	0	0
T2	221595	18793	0	0
T3	112602	832	0	0
T4	1321724	15391	0	0
T5	898	0	0	0
T6	8545	832	0	0
T7	888249	9983	0	0
T8	3380	0	0	0
T9	203387	832	0	0
T10	666587	0	0	0
T11	53376	1992	0	0
T12	196150	3468	0	0
T13	234586	832	0	0
T24	1149	0	0	0
T25	68212	0	0	0
T26	59602	1102	0	0
T27	0	1987	0	0
T28	0	5033	0	0
T29	0	4798	0	0
T30	0	2465	0	0
T37	0	4961	0	0
T38	0	4274	0	0
T42	0	1663	0	0
T45	0	2	0	0
T47	0	1495	0	0
T52	0	2152	0	0
T53	0	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745897527	3668320	0	0
T2	221595	18793	0	0
T3	112602	832	0	0
T4	1321724	15391	0	0
T5	898	0	0	0
T6	8545	832	0	0
T7	888249	9983	0	0
T8	3380	0	0	0
T9	203387	832	0	0
T10	666587	0	0	0
T11	53376	1992	0	0
T12	196150	3468	0	0
T13	234586	832	0	0
T24	1149	0	0	0
T25	68212	0	0	0
T26	59602	1102	0	0
T27	0	1987	0	0
T28	0	5033	0	0
T29	0	4798	0	0
T30	0	2465	0	0
T37	0	4961	0	0
T38	0	4274	0	0
T42	0	1663	0	0
T45	0	2	0	0
T47	0	1495	0	0
T52	0	2152	0	0
T53	0	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745897527	3668320	0	0
T2	221595	18793	0	0
T3	112602	832	0	0
T4	1321724	15391	0	0
T5	898	0	0	0
T6	8545	832	0	0
T7	888249	9983	0	0
T8	3380	0	0	0
T9	203387	832	0	0
T10	666587	0	0	0
T11	53376	1992	0	0
T12	196150	3468	0	0
T13	234586	832	0	0
T24	1149	0	0	0
T25	68212	0	0	0
T26	59602	1102	0	0
T27	0	1987	0	0
T28	0	5033	0	0
T29	0	4798	0	0
T30	0	2465	0	0
T37	0	4961	0	0
T38	0	4274	0	0
T42	0	1663	0	0
T45	0	2	0	0
T47	0	1495	0	0
T52	0	2152	0	0
T53	0	4	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	745897527	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745897527	5	0	975
T54	590363	1	0	1
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	481885	0	0	1
T60	12067	0	0	1
T61	40350	0	0	1
T62	180395	0	0	1
T63	555125	0	0	1
T64	529077	0	0	1
T65	14497	0	0	1
T66	3755	0	0	1
T67	101913	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745897527	593214069	0	0
T1	1087	1023	0	0
T2	221595	221348	0	0
T3	112602	111887	0	0
T4	1321724	883619	0	0
T5	898	822	0	0
T6	8545	8429	0	0
T7	888249	497438	0	0
T8	3380	3133	0	0
T9	203387	114178	0	0
T10	666587	581786	0	0
T11	53376	26688	0	0
T12	196150	95755	0	0
T13	234586	116618	0	0
T14	0	192	0	0
T25	68212	64208	0	0
T26	59602	59104	0	0
T27	0	45872	0	0
T28	0	198336	0	0
T29	0	246448	0	0
T30	0	96272	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745897527	3668320	0	0
T2	221595	18793	0	0
T3	112602	832	0	0
T4	1321724	15391	0	0
T5	898	0	0	0
T6	8545	832	0	0
T7	888249	9983	0	0
T8	3380	0	0	0
T9	203387	832	0	0
T10	666587	0	0	0
T11	53376	1992	0	0
T12	196150	3468	0	0
T13	234586	832	0	0
T24	1149	0	0	0
T25	68212	0	0	0
T26	59602	1102	0	0
T27	0	1987	0	0
T28	0	5033	0	0
T29	0	4798	0	0
T30	0	2465	0	0
T37	0	4961	0	0
T38	0	4274	0	0
T42	0	1663	0	0
T45	0	2	0	0
T47	0	1495	0	0
T52	0	2152	0	0
T53	0	4	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T12
1	0	Covered	T4,T7,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T10
1	0	Unreachable
1	1	Covered	T4,T7,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T7,T12
0	0	1	Unreachable
0	0	0	Covered	T4,T7,T10

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	151328091	25106353	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	151328091	567028	0	0
GntImpliesValid_A	151328091	567028	0	0
GrantKnown_A	151328091	25106353	0	0
IdxKnown_A	151328091	25106353	0	0
IndexIsCorrect_A	151328091	567028	0	0
LockArbDecision_A	151328091	0	0	0
NoReadyValidNoGrant_A	151328091	0	0	0
ReadyAndValidImplyGrant_A	151328091	567028	0	0
ReqAndReadyImplyGrant_A	151328091	567028	0	0
ReqImpliesValid_A	151328091	567028	0	0
ReqStaysHighUntilGranted0_M	151328091	0	0	0
RoundRobin_A	151328091	0	0	0
ValidKnown_A	151328091	25106353	0	0
gen_data_port_assertion.DataFlow_A	151328091	567028	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151328091	25106353	0	0
T4	429229	149984	0	0
T6	16	0	0	0
T7	386033	48792	0	0
T9	88291	0	0	0
T10	79869	75008	0	0
T11	26688	0	0	0
T12	98075	44112	0	0
T13	117293	0	0	0
T25	68212	64208	0	0
T26	59602	59104	0	0
T27	0	45872	0	0
T28	0	198336	0	0
T29	0	246448	0	0
T30	0	96272	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151328091	567028	0	0
T4	429229	3734	0	0
T6	16	0	0	0
T7	386033	2083	0	0
T9	88291	0	0	0
T10	79869	0	0	0
T11	26688	0	0	0
T12	98075	1697	0	0
T13	117293	0	0	0
T25	68212	0	0	0
T26	59602	762	0	0
T27	0	1987	0	0
T28	0	5033	0	0
T29	0	4798	0	0
T30	0	2465	0	0
T47	0	1495	0	0
T52	0	1200	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151328091	567028	0	0
T4	429229	3734	0	0
T6	16	0	0	0
T7	386033	2083	0	0
T9	88291	0	0	0
T10	79869	0	0	0
T11	26688	0	0	0
T12	98075	1697	0	0
T13	117293	0	0	0
T25	68212	0	0	0
T26	59602	762	0	0
T27	0	1987	0	0
T28	0	5033	0	0
T29	0	4798	0	0
T30	0	2465	0	0
T47	0	1495	0	0
T52	0	1200	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151328091	25106353	0	0
T4	429229	149984	0	0
T6	16	0	0	0
T7	386033	48792	0	0
T9	88291	0	0	0
T10	79869	75008	0	0
T11	26688	0	0	0
T12	98075	44112	0	0
T13	117293	0	0	0
T25	68212	64208	0	0
T26	59602	59104	0	0
T27	0	45872	0	0
T28	0	198336	0	0
T29	0	246448	0	0
T30	0	96272	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151328091	25106353	0	0
T4	429229	149984	0	0
T6	16	0	0	0
T7	386033	48792	0	0
T9	88291	0	0	0
T10	79869	75008	0	0
T11	26688	0	0	0
T12	98075	44112	0	0
T13	117293	0	0	0
T25	68212	64208	0	0
T26	59602	59104	0	0
T27	0	45872	0	0
T28	0	198336	0	0
T29	0	246448	0	0
T30	0	96272	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151328091	567028	0	0
T4	429229	3734	0	0
T6	16	0	0	0
T7	386033	2083	0	0
T9	88291	0	0	0
T10	79869	0	0	0
T11	26688	0	0	0
T12	98075	1697	0	0
T13	117293	0	0	0
T25	68212	0	0	0
T26	59602	762	0	0
T27	0	1987	0	0
T28	0	5033	0	0
T29	0	4798	0	0
T30	0	2465	0	0
T47	0	1495	0	0
T52	0	1200	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151328091	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151328091	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151328091	567028	0	0
T4	429229	3734	0	0
T6	16	0	0	0
T7	386033	2083	0	0
T9	88291	0	0	0
T10	79869	0	0	0
T11	26688	0	0	0
T12	98075	1697	0	0
T13	117293	0	0	0
T25	68212	0	0	0
T26	59602	762	0	0
T27	0	1987	0	0
T28	0	5033	0	0
T29	0	4798	0	0
T30	0	2465	0	0
T47	0	1495	0	0
T52	0	1200	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151328091	567028	0	0
T4	429229	3734	0	0
T6	16	0	0	0
T7	386033	2083	0	0
T9	88291	0	0	0
T10	79869	0	0	0
T11	26688	0	0	0
T12	98075	1697	0	0
T13	117293	0	0	0
T25	68212	0	0	0
T26	59602	762	0	0
T27	0	1987	0	0
T28	0	5033	0	0
T29	0	4798	0	0
T30	0	2465	0	0
T47	0	1495	0	0
T52	0	1200	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151328091	567028	0	0
T4	429229	3734	0	0
T6	16	0	0	0
T7	386033	2083	0	0
T9	88291	0	0	0
T10	79869	0	0	0
T11	26688	0	0	0
T12	98075	1697	0	0
T13	117293	0	0	0
T25	68212	0	0	0
T26	59602	762	0	0
T27	0	1987	0	0
T28	0	5033	0	0
T29	0	4798	0	0
T30	0	2465	0	0
T47	0	1495	0	0
T52	0	1200	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	151328091	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151328091	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151328091	25106353	0	0
T4	429229	149984	0	0
T6	16	0	0	0
T7	386033	48792	0	0
T9	88291	0	0	0
T10	79869	75008	0	0
T11	26688	0	0	0
T12	98075	44112	0	0
T13	117293	0	0	0
T25	68212	64208	0	0
T26	59602	59104	0	0
T27	0	45872	0	0
T28	0	198336	0	0
T29	0	246448	0	0
T30	0	96272	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151328091	567028	0	0
T4	429229	3734	0	0
T6	16	0	0	0
T7	386033	2083	0	0
T9	88291	0	0	0
T10	79869	0	0	0
T11	26688	0	0	0
T12	98075	1697	0	0
T13	117293	0	0	0
T25	68212	0	0	0
T26	59602	762	0	0
T27	0	1987	0	0
T28	0	5033	0	0
T29	0	4798	0	0
T30	0	2465	0	0
T47	0	1495	0	0
T52	0	1200	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T7
1	0	Covered	T2,T4,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T2,T4,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T7
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	151328091	124955499	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	151328091	892901	0	0
GntImpliesValid_A	151328091	892901	0	0
GrantKnown_A	151328091	124955499	0	0
IdxKnown_A	151328091	124955499	0	0
IndexIsCorrect_A	151328091	892901	0	0
LockArbDecision_A	151328091	0	0	0
NoReadyValidNoGrant_A	151328091	0	0	0
ReadyAndValidImplyGrant_A	151328091	892901	0	0
ReqAndReadyImplyGrant_A	151328091	892901	0	0
ReqImpliesValid_A	151328091	892901	0	0
ReqStaysHighUntilGranted0_M	151328091	0	0	0
RoundRobin_A	151328091	0	0	0
ValidKnown_A	151328091	124955499	0	0
gen_data_port_assertion.DataFlow_A	151328091	892901	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151328091	124955499	0	0
T2	105377	105136	0	0
T3	51802	51148	0	0
T4	429229	270466	0	0
T6	16	16	0	0
T7	386033	332470	0	0
T9	88291	87466	0	0
T10	79869	0	0	0
T11	26688	26688	0	0
T12	98075	51643	0	0
T13	117293	116618	0	0
T14	0	192	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151328091	892901	0	0
T2	105377	8309	0	0
T3	51802	0	0	0
T4	429229	3808	0	0
T6	16	0	0	0
T7	386033	3423	0	0
T9	88291	0	0	0
T10	79869	0	0	0
T11	26688	1028	0	0
T12	98075	0	0	0
T13	117293	0	0	0
T37	0	4961	0	0
T38	0	4274	0	0
T42	0	1663	0	0
T45	0	2	0	0
T52	0	952	0	0
T53	0	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151328091	892901	0	0
T2	105377	8309	0	0
T3	51802	0	0	0
T4	429229	3808	0	0
T6	16	0	0	0
T7	386033	3423	0	0
T9	88291	0	0	0
T10	79869	0	0	0
T11	26688	1028	0	0
T12	98075	0	0	0
T13	117293	0	0	0
T37	0	4961	0	0
T38	0	4274	0	0
T42	0	1663	0	0
T45	0	2	0	0
T52	0	952	0	0
T53	0	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151328091	124955499	0	0
T2	105377	105136	0	0
T3	51802	51148	0	0
T4	429229	270466	0	0
T6	16	16	0	0
T7	386033	332470	0	0
T9	88291	87466	0	0
T10	79869	0	0	0
T11	26688	26688	0	0
T12	98075	51643	0	0
T13	117293	116618	0	0
T14	0	192	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151328091	124955499	0	0
T2	105377	105136	0	0
T3	51802	51148	0	0
T4	429229	270466	0	0
T6	16	16	0	0
T7	386033	332470	0	0
T9	88291	87466	0	0
T10	79869	0	0	0
T11	26688	26688	0	0
T12	98075	51643	0	0
T13	117293	116618	0	0
T14	0	192	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151328091	892901	0	0
T2	105377	8309	0	0
T3	51802	0	0	0
T4	429229	3808	0	0
T6	16	0	0	0
T7	386033	3423	0	0
T9	88291	0	0	0
T10	79869	0	0	0
T11	26688	1028	0	0
T12	98075	0	0	0
T13	117293	0	0	0
T37	0	4961	0	0
T38	0	4274	0	0
T42	0	1663	0	0
T45	0	2	0	0
T52	0	952	0	0
T53	0	4	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151328091	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151328091	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151328091	892901	0	0
T2	105377	8309	0	0
T3	51802	0	0	0
T4	429229	3808	0	0
T6	16	0	0	0
T7	386033	3423	0	0
T9	88291	0	0	0
T10	79869	0	0	0
T11	26688	1028	0	0
T12	98075	0	0	0
T13	117293	0	0	0
T37	0	4961	0	0
T38	0	4274	0	0
T42	0	1663	0	0
T45	0	2	0	0
T52	0	952	0	0
T53	0	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151328091	892901	0	0
T2	105377	8309	0	0
T3	51802	0	0	0
T4	429229	3808	0	0
T6	16	0	0	0
T7	386033	3423	0	0
T9	88291	0	0	0
T10	79869	0	0	0
T11	26688	1028	0	0
T12	98075	0	0	0
T13	117293	0	0	0
T37	0	4961	0	0
T38	0	4274	0	0
T42	0	1663	0	0
T45	0	2	0	0
T52	0	952	0	0
T53	0	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151328091	892901	0	0
T2	105377	8309	0	0
T3	51802	0	0	0
T4	429229	3808	0	0
T6	16	0	0	0
T7	386033	3423	0	0
T9	88291	0	0	0
T10	79869	0	0	0
T11	26688	1028	0	0
T12	98075	0	0	0
T13	117293	0	0	0
T37	0	4961	0	0
T38	0	4274	0	0
T42	0	1663	0	0
T45	0	2	0	0
T52	0	952	0	0
T53	0	4	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	151328091	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151328091	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151328091	124955499	0	0
T2	105377	105136	0	0
T3	51802	51148	0	0
T4	429229	270466	0	0
T6	16	16	0	0
T7	386033	332470	0	0
T9	88291	87466	0	0
T10	79869	0	0	0
T11	26688	26688	0	0
T12	98075	51643	0	0
T13	117293	116618	0	0
T14	0	192	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151328091	892901	0	0
T2	105377	8309	0	0
T3	51802	0	0	0
T4	429229	3808	0	0
T6	16	0	0	0
T7	386033	3423	0	0
T9	88291	0	0	0
T10	79869	0	0	0
T11	26688	1028	0	0
T12	98075	0	0	0
T13	117293	0	0	0
T37	0	4961	0	0
T38	0	4274	0	0
T42	0	1663	0	0
T45	0	2	0	0
T52	0	952	0	0
T53	0	4	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T7
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443241345	443152217	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	443241345	2208391	0	0
GntImpliesValid_A	443241345	2208391	0	0
GrantKnown_A	443241345	443152217	0	0
IdxKnown_A	443241345	443152217	0	0
IndexIsCorrect_A	443241345	2208391	0	0
LockArbDecision_A	443241345	0	0	0
NoReadyValidNoGrant_A	443241345	0	0	0
ReadyAndValidImplyGrant_A	443241345	2208391	0	0
ReqAndReadyImplyGrant_A	443241345	2208391	0	0
ReqImpliesValid_A	443241345	2208391	0	0
ReqStaysHighUntilGranted0_M	443241345	0	0	0
RoundRobin_A	443241345	5	0	975
ValidKnown_A	443241345	443152217	0	0
gen_data_port_assertion.DataFlow_A	443241345	2208391	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443241345	443152217	0	0
T1	1087	1023	0	0
T2	116218	116212	0	0
T3	60800	60739	0	0
T4	463266	463169	0	0
T5	898	822	0	0
T6	8513	8413	0	0
T7	116183	116176	0	0
T8	3380	3133	0	0
T9	26805	26712	0	0
T10	506849	506778	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443241345	2208391	0	0
T2	116218	10484	0	0
T3	60800	832	0	0
T4	463266	7849	0	0
T5	898	0	0	0
T6	8513	832	0	0
T7	116183	4477	0	0
T8	3380	0	0	0
T9	26805	832	0	0
T10	506849	0	0	0
T11	0	964	0	0
T12	0	1771	0	0
T13	0	832	0	0
T24	1149	0	0	0
T26	0	340	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443241345	2208391	0	0
T2	116218	10484	0	0
T3	60800	832	0	0
T4	463266	7849	0	0
T5	898	0	0	0
T6	8513	832	0	0
T7	116183	4477	0	0
T8	3380	0	0	0
T9	26805	832	0	0
T10	506849	0	0	0
T11	0	964	0	0
T12	0	1771	0	0
T13	0	832	0	0
T24	1149	0	0	0
T26	0	340	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443241345	443152217	0	0
T1	1087	1023	0	0
T2	116218	116212	0	0
T3	60800	60739	0	0
T4	463266	463169	0	0
T5	898	822	0	0
T6	8513	8413	0	0
T7	116183	116176	0	0
T8	3380	3133	0	0
T9	26805	26712	0	0
T10	506849	506778	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443241345	443152217	0	0
T1	1087	1023	0	0
T2	116218	116212	0	0
T3	60800	60739	0	0
T4	463266	463169	0	0
T5	898	822	0	0
T6	8513	8413	0	0
T7	116183	116176	0	0
T8	3380	3133	0	0
T9	26805	26712	0	0
T10	506849	506778	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443241345	2208391	0	0
T2	116218	10484	0	0
T3	60800	832	0	0
T4	463266	7849	0	0
T5	898	0	0	0
T6	8513	832	0	0
T7	116183	4477	0	0
T8	3380	0	0	0
T9	26805	832	0	0
T10	506849	0	0	0
T11	0	964	0	0
T12	0	1771	0	0
T13	0	832	0	0
T24	1149	0	0	0
T26	0	340	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443241345	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443241345	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443241345	2208391	0	0
T2	116218	10484	0	0
T3	60800	832	0	0
T4	463266	7849	0	0
T5	898	0	0	0
T6	8513	832	0	0
T7	116183	4477	0	0
T8	3380	0	0	0
T9	26805	832	0	0
T10	506849	0	0	0
T11	0	964	0	0
T12	0	1771	0	0
T13	0	832	0	0
T24	1149	0	0	0
T26	0	340	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443241345	2208391	0	0
T2	116218	10484	0	0
T3	60800	832	0	0
T4	463266	7849	0	0
T5	898	0	0	0
T6	8513	832	0	0
T7	116183	4477	0	0
T8	3380	0	0	0
T9	26805	832	0	0
T10	506849	0	0	0
T11	0	964	0	0
T12	0	1771	0	0
T13	0	832	0	0
T24	1149	0	0	0
T26	0	340	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443241345	2208391	0	0
T2	116218	10484	0	0
T3	60800	832	0	0
T4	463266	7849	0	0
T5	898	0	0	0
T6	8513	832	0	0
T7	116183	4477	0	0
T8	3380	0	0	0
T9	26805	832	0	0
T10	506849	0	0	0
T11	0	964	0	0
T12	0	1771	0	0
T13	0	832	0	0
T24	1149	0	0	0
T26	0	340	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443241345	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443241345	5	0	975
T54	590363	1	0	1
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	481885	0	0	1
T60	12067	0	0	1
T61	40350	0	0	1
T62	180395	0	0	1
T63	555125	0	0	1
T64	529077	0	0	1
T65	14497	0	0	1
T66	3755	0	0	1
T67	101913	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443241345	443152217	0	0
T1	1087	1023	0	0
T2	116218	116212	0	0
T3	60800	60739	0	0
T4	463266	463169	0	0
T5	898	822	0	0
T6	8513	8413	0	0
T7	116183	116176	0	0
T8	3380	3133	0	0
T9	26805	26712	0	0
T10	506849	506778	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443241345	2208391	0	0
T2	116218	10484	0	0
T3	60800	832	0	0
T4	463266	7849	0	0
T5	898	0	0	0
T6	8513	832	0	0
T7	116183	4477	0	0
T8	3380	0	0	0
T9	26805	832	0	0
T10	506849	0	0	0
T11	0	964	0	0
T12	0	1771	0	0
T13	0	832	0	0
T24	1149	0	0	0
T26	0	340	0	0