Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
3578 |
0 |
0 |
T97 |
5028 |
50 |
0 |
0 |
T98 |
2365 |
5 |
0 |
0 |
T99 |
29287 |
4 |
0 |
0 |
T100 |
4248 |
114 |
0 |
0 |
T101 |
7822 |
321 |
0 |
0 |
T102 |
9747 |
1 |
0 |
0 |
T108 |
7744 |
105 |
0 |
0 |
T117 |
10784 |
7 |
0 |
0 |
T118 |
6106 |
3 |
0 |
0 |
T119 |
9601 |
1 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
2807 |
0 |
0 |
T85 |
3194 |
5 |
0 |
0 |
T103 |
98439 |
114 |
0 |
0 |
T117 |
10784 |
6 |
0 |
0 |
T118 |
6106 |
7 |
0 |
0 |
T119 |
9601 |
20 |
0 |
0 |
T128 |
180077 |
530 |
0 |
0 |
T132 |
8449 |
11 |
0 |
0 |
T155 |
3691 |
8 |
0 |
0 |
T156 |
5561 |
11 |
0 |
0 |
T157 |
11723 |
7 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
2860 |
0 |
0 |
T85 |
3194 |
9 |
0 |
0 |
T103 |
98439 |
109 |
0 |
0 |
T117 |
10784 |
11 |
0 |
0 |
T118 |
6106 |
7 |
0 |
0 |
T119 |
9601 |
4 |
0 |
0 |
T128 |
180077 |
516 |
0 |
0 |
T132 |
8449 |
9 |
0 |
0 |
T156 |
5561 |
5 |
0 |
0 |
T157 |
11723 |
12 |
0 |
0 |
T158 |
14761 |
19 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
3253 |
0 |
0 |
T85 |
3194 |
10 |
0 |
0 |
T103 |
98439 |
248 |
0 |
0 |
T117 |
10784 |
18 |
0 |
0 |
T118 |
6106 |
10 |
0 |
0 |
T119 |
9601 |
19 |
0 |
0 |
T122 |
3641 |
3 |
0 |
0 |
T128 |
180077 |
394 |
0 |
0 |
T132 |
8449 |
6 |
0 |
0 |
T155 |
3691 |
8 |
0 |
0 |
T156 |
5561 |
10 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
11570 |
0 |
0 |
T85 |
3194 |
10 |
0 |
0 |
T103 |
98439 |
1707 |
0 |
0 |
T117 |
10784 |
144 |
0 |
0 |
T118 |
6106 |
12 |
0 |
0 |
T119 |
9601 |
118 |
0 |
0 |
T122 |
3641 |
1 |
0 |
0 |
T128 |
180077 |
486 |
0 |
0 |
T132 |
8449 |
246 |
0 |
0 |
T155 |
3691 |
2 |
0 |
0 |
T156 |
5561 |
11 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
10748 |
0 |
0 |
T85 |
3194 |
9 |
0 |
0 |
T103 |
98439 |
1896 |
0 |
0 |
T117 |
10784 |
143 |
0 |
0 |
T118 |
6106 |
7 |
0 |
0 |
T119 |
9601 |
120 |
0 |
0 |
T122 |
3641 |
59 |
0 |
0 |
T128 |
180077 |
421 |
0 |
0 |
T132 |
8449 |
236 |
0 |
0 |
T155 |
3691 |
135 |
0 |
0 |
T156 |
5561 |
142 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
11020 |
0 |
0 |
T85 |
3194 |
7 |
0 |
0 |
T103 |
98439 |
2288 |
0 |
0 |
T116 |
9381 |
4 |
0 |
0 |
T117 |
10784 |
120 |
0 |
0 |
T118 |
6106 |
126 |
0 |
0 |
T119 |
9601 |
77 |
0 |
0 |
T128 |
180077 |
415 |
0 |
0 |
T132 |
8449 |
216 |
0 |
0 |
T155 |
3691 |
111 |
0 |
0 |
T156 |
5561 |
15 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
10187 |
0 |
0 |
T85 |
3194 |
3 |
0 |
0 |
T103 |
98439 |
1592 |
0 |
0 |
T117 |
10784 |
131 |
0 |
0 |
T118 |
6106 |
131 |
0 |
0 |
T119 |
9601 |
47 |
0 |
0 |
T122 |
3641 |
79 |
0 |
0 |
T128 |
180077 |
499 |
0 |
0 |
T132 |
8449 |
221 |
0 |
0 |
T155 |
3691 |
3 |
0 |
0 |
T156 |
5561 |
5 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
11911 |
0 |
0 |
T85 |
3194 |
4 |
0 |
0 |
T103 |
98439 |
1825 |
0 |
0 |
T117 |
10784 |
239 |
0 |
0 |
T118 |
6106 |
3 |
0 |
0 |
T119 |
9601 |
13 |
0 |
0 |
T122 |
3641 |
91 |
0 |
0 |
T128 |
180077 |
432 |
0 |
0 |
T132 |
8449 |
99 |
0 |
0 |
T155 |
3691 |
4 |
0 |
0 |
T156 |
5561 |
139 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
11240 |
0 |
0 |
T85 |
3194 |
6 |
0 |
0 |
T103 |
98439 |
1889 |
0 |
0 |
T117 |
10784 |
23 |
0 |
0 |
T118 |
6106 |
118 |
0 |
0 |
T119 |
9601 |
75 |
0 |
0 |
T128 |
180077 |
436 |
0 |
0 |
T132 |
8449 |
15 |
0 |
0 |
T155 |
3691 |
9 |
0 |
0 |
T156 |
5561 |
109 |
0 |
0 |
T157 |
11723 |
138 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
10467 |
0 |
0 |
T85 |
3194 |
3 |
0 |
0 |
T103 |
98439 |
1337 |
0 |
0 |
T117 |
10784 |
105 |
0 |
0 |
T118 |
6106 |
103 |
0 |
0 |
T119 |
9601 |
63 |
0 |
0 |
T128 |
180077 |
465 |
0 |
0 |
T132 |
8449 |
136 |
0 |
0 |
T155 |
3691 |
133 |
0 |
0 |
T156 |
5561 |
9 |
0 |
0 |
T157 |
11723 |
288 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
9527 |
0 |
0 |
T103 |
98439 |
1725 |
0 |
0 |
T117 |
10784 |
111 |
0 |
0 |
T118 |
6106 |
7 |
0 |
0 |
T119 |
9601 |
155 |
0 |
0 |
T122 |
3641 |
43 |
0 |
0 |
T128 |
180077 |
471 |
0 |
0 |
T132 |
8449 |
120 |
0 |
0 |
T155 |
3691 |
101 |
0 |
0 |
T156 |
5561 |
8 |
0 |
0 |
T157 |
11723 |
145 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
5452 |
0 |
0 |
T85 |
3194 |
9 |
0 |
0 |
T103 |
98439 |
448 |
0 |
0 |
T117 |
10784 |
16 |
0 |
0 |
T118 |
6106 |
7 |
0 |
0 |
T119 |
9601 |
23 |
0 |
0 |
T122 |
3641 |
3 |
0 |
0 |
T128 |
180077 |
405 |
0 |
0 |
T132 |
8449 |
17 |
0 |
0 |
T155 |
3691 |
48 |
0 |
0 |
T156 |
5561 |
57 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
6486 |
0 |
0 |
T85 |
3194 |
2 |
0 |
0 |
T103 |
98439 |
1013 |
0 |
0 |
T109 |
12201 |
5 |
0 |
0 |
T117 |
10784 |
69 |
0 |
0 |
T118 |
6106 |
60 |
0 |
0 |
T119 |
9601 |
34 |
0 |
0 |
T128 |
180077 |
456 |
0 |
0 |
T132 |
8449 |
38 |
0 |
0 |
T155 |
3691 |
9 |
0 |
0 |
T156 |
5561 |
58 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
6279 |
0 |
0 |
T85 |
3194 |
7 |
0 |
0 |
T103 |
98439 |
982 |
0 |
0 |
T117 |
10784 |
26 |
0 |
0 |
T118 |
6106 |
55 |
0 |
0 |
T119 |
9601 |
15 |
0 |
0 |
T122 |
3641 |
25 |
0 |
0 |
T128 |
180077 |
434 |
0 |
0 |
T132 |
8449 |
42 |
0 |
0 |
T155 |
3691 |
1 |
0 |
0 |
T156 |
5561 |
42 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
6191 |
0 |
0 |
T85 |
3194 |
10 |
0 |
0 |
T103 |
98439 |
686 |
0 |
0 |
T117 |
10784 |
9 |
0 |
0 |
T118 |
6106 |
52 |
0 |
0 |
T119 |
9601 |
38 |
0 |
0 |
T128 |
180077 |
476 |
0 |
0 |
T132 |
8449 |
48 |
0 |
0 |
T155 |
3691 |
64 |
0 |
0 |
T156 |
5561 |
46 |
0 |
0 |
T157 |
11723 |
87 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
5795 |
0 |
0 |
T85 |
3194 |
5 |
0 |
0 |
T103 |
98439 |
660 |
0 |
0 |
T117 |
10784 |
64 |
0 |
0 |
T118 |
6106 |
9 |
0 |
0 |
T119 |
9601 |
2 |
0 |
0 |
T122 |
3641 |
11 |
0 |
0 |
T128 |
180077 |
428 |
0 |
0 |
T132 |
8449 |
7 |
0 |
0 |
T155 |
3691 |
7 |
0 |
0 |
T156 |
5561 |
4 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
6122 |
0 |
0 |
T85 |
3194 |
3 |
0 |
0 |
T103 |
98439 |
870 |
0 |
0 |
T117 |
10784 |
64 |
0 |
0 |
T118 |
6106 |
1 |
0 |
0 |
T119 |
9601 |
18 |
0 |
0 |
T122 |
3641 |
22 |
0 |
0 |
T128 |
180077 |
452 |
0 |
0 |
T132 |
8449 |
90 |
0 |
0 |
T155 |
3691 |
3 |
0 |
0 |
T156 |
5561 |
9 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
5766 |
0 |
0 |
T85 |
3194 |
8 |
0 |
0 |
T103 |
98439 |
900 |
0 |
0 |
T109 |
12201 |
8 |
0 |
0 |
T117 |
10784 |
72 |
0 |
0 |
T118 |
6106 |
5 |
0 |
0 |
T119 |
9601 |
7 |
0 |
0 |
T122 |
3641 |
18 |
0 |
0 |
T128 |
180077 |
484 |
0 |
0 |
T155 |
3691 |
6 |
0 |
0 |
T156 |
5561 |
12 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
5906 |
0 |
0 |
T85 |
3194 |
6 |
0 |
0 |
T103 |
98439 |
730 |
0 |
0 |
T117 |
10784 |
111 |
0 |
0 |
T118 |
6106 |
11 |
0 |
0 |
T119 |
9601 |
19 |
0 |
0 |
T122 |
3641 |
25 |
0 |
0 |
T128 |
180077 |
445 |
0 |
0 |
T132 |
8449 |
57 |
0 |
0 |
T155 |
3691 |
45 |
0 |
0 |
T156 |
5561 |
55 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
6153 |
0 |
0 |
T85 |
3194 |
4 |
0 |
0 |
T103 |
98439 |
677 |
0 |
0 |
T117 |
10784 |
63 |
0 |
0 |
T118 |
6106 |
69 |
0 |
0 |
T119 |
9601 |
36 |
0 |
0 |
T122 |
3641 |
27 |
0 |
0 |
T128 |
180077 |
442 |
0 |
0 |
T132 |
8449 |
40 |
0 |
0 |
T155 |
3691 |
74 |
0 |
0 |
T156 |
5561 |
44 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
5780 |
0 |
0 |
T85 |
3194 |
6 |
0 |
0 |
T103 |
98439 |
746 |
0 |
0 |
T117 |
10784 |
57 |
0 |
0 |
T118 |
6106 |
63 |
0 |
0 |
T119 |
9601 |
60 |
0 |
0 |
T122 |
3641 |
59 |
0 |
0 |
T128 |
180077 |
445 |
0 |
0 |
T132 |
8449 |
65 |
0 |
0 |
T155 |
3691 |
3 |
0 |
0 |
T156 |
5561 |
14 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
5208 |
0 |
0 |
T85 |
3194 |
4 |
0 |
0 |
T103 |
98439 |
821 |
0 |
0 |
T117 |
10784 |
10 |
0 |
0 |
T119 |
9601 |
9 |
0 |
0 |
T122 |
3641 |
26 |
0 |
0 |
T128 |
180077 |
437 |
0 |
0 |
T132 |
8449 |
51 |
0 |
0 |
T155 |
3691 |
6 |
0 |
0 |
T156 |
5561 |
8 |
0 |
0 |
T157 |
11723 |
61 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
6124 |
0 |
0 |
T85 |
3194 |
11 |
0 |
0 |
T103 |
98439 |
690 |
0 |
0 |
T117 |
10784 |
16 |
0 |
0 |
T118 |
6106 |
68 |
0 |
0 |
T119 |
9601 |
16 |
0 |
0 |
T122 |
3641 |
2 |
0 |
0 |
T128 |
180077 |
463 |
0 |
0 |
T132 |
8449 |
1 |
0 |
0 |
T155 |
3691 |
67 |
0 |
0 |
T156 |
5561 |
60 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
5826 |
0 |
0 |
T85 |
3194 |
3 |
0 |
0 |
T103 |
98439 |
712 |
0 |
0 |
T117 |
10784 |
100 |
0 |
0 |
T118 |
6106 |
63 |
0 |
0 |
T119 |
9601 |
22 |
0 |
0 |
T122 |
3641 |
1 |
0 |
0 |
T128 |
180077 |
453 |
0 |
0 |
T132 |
8449 |
51 |
0 |
0 |
T155 |
3691 |
5 |
0 |
0 |
T156 |
5561 |
9 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
6028 |
0 |
0 |
T85 |
3194 |
7 |
0 |
0 |
T103 |
98439 |
971 |
0 |
0 |
T108 |
7744 |
7 |
0 |
0 |
T117 |
10784 |
70 |
0 |
0 |
T118 |
6106 |
9 |
0 |
0 |
T119 |
9601 |
27 |
0 |
0 |
T122 |
3641 |
1 |
0 |
0 |
T128 |
180077 |
474 |
0 |
0 |
T155 |
3691 |
43 |
0 |
0 |
T156 |
5561 |
10 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
6243 |
0 |
0 |
T85 |
3194 |
10 |
0 |
0 |
T103 |
98439 |
1002 |
0 |
0 |
T117 |
10784 |
47 |
0 |
0 |
T118 |
6106 |
10 |
0 |
0 |
T119 |
9601 |
37 |
0 |
0 |
T122 |
3641 |
10 |
0 |
0 |
T128 |
180077 |
387 |
0 |
0 |
T132 |
8449 |
78 |
0 |
0 |
T155 |
3691 |
41 |
0 |
0 |
T156 |
5561 |
54 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
6070 |
0 |
0 |
T85 |
3194 |
10 |
0 |
0 |
T103 |
98439 |
965 |
0 |
0 |
T117 |
10784 |
90 |
0 |
0 |
T118 |
6106 |
11 |
0 |
0 |
T119 |
9601 |
73 |
0 |
0 |
T128 |
180077 |
501 |
0 |
0 |
T132 |
8449 |
10 |
0 |
0 |
T155 |
3691 |
74 |
0 |
0 |
T156 |
5561 |
53 |
0 |
0 |
T157 |
11723 |
55 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
6283 |
0 |
0 |
T85 |
3194 |
3 |
0 |
0 |
T103 |
98439 |
781 |
0 |
0 |
T117 |
10784 |
56 |
0 |
0 |
T118 |
6106 |
9 |
0 |
0 |
T119 |
9601 |
56 |
0 |
0 |
T128 |
180077 |
441 |
0 |
0 |
T132 |
8449 |
16 |
0 |
0 |
T155 |
3691 |
73 |
0 |
0 |
T156 |
5561 |
56 |
0 |
0 |
T157 |
11723 |
65 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
6085 |
0 |
0 |
T85 |
3194 |
11 |
0 |
0 |
T103 |
98439 |
964 |
0 |
0 |
T117 |
10784 |
107 |
0 |
0 |
T118 |
6106 |
6 |
0 |
0 |
T119 |
9601 |
1 |
0 |
0 |
T122 |
3641 |
27 |
0 |
0 |
T128 |
180077 |
428 |
0 |
0 |
T155 |
3691 |
4 |
0 |
0 |
T156 |
5561 |
52 |
0 |
0 |
T157 |
11723 |
122 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
6159 |
0 |
0 |
T85 |
3194 |
9 |
0 |
0 |
T103 |
98439 |
840 |
0 |
0 |
T117 |
10784 |
120 |
0 |
0 |
T118 |
6106 |
76 |
0 |
0 |
T119 |
9601 |
7 |
0 |
0 |
T122 |
3641 |
18 |
0 |
0 |
T128 |
180077 |
417 |
0 |
0 |
T132 |
8449 |
110 |
0 |
0 |
T155 |
3691 |
1 |
0 |
0 |
T156 |
5561 |
54 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
6042 |
0 |
0 |
T85 |
3194 |
3 |
0 |
0 |
T103 |
98439 |
867 |
0 |
0 |
T117 |
10784 |
53 |
0 |
0 |
T118 |
6106 |
5 |
0 |
0 |
T119 |
9601 |
24 |
0 |
0 |
T122 |
3641 |
28 |
0 |
0 |
T128 |
180077 |
428 |
0 |
0 |
T132 |
8449 |
105 |
0 |
0 |
T155 |
3691 |
5 |
0 |
0 |
T156 |
5561 |
7 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
6032 |
0 |
0 |
T85 |
3194 |
10 |
0 |
0 |
T103 |
98439 |
702 |
0 |
0 |
T117 |
10784 |
124 |
0 |
0 |
T118 |
6106 |
55 |
0 |
0 |
T119 |
9601 |
79 |
0 |
0 |
T128 |
180077 |
389 |
0 |
0 |
T132 |
8449 |
83 |
0 |
0 |
T155 |
3691 |
4 |
0 |
0 |
T156 |
5561 |
54 |
0 |
0 |
T157 |
11723 |
43 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
5949 |
0 |
0 |
T85 |
3194 |
10 |
0 |
0 |
T103 |
98439 |
758 |
0 |
0 |
T117 |
10784 |
70 |
0 |
0 |
T118 |
6106 |
6 |
0 |
0 |
T119 |
9601 |
5 |
0 |
0 |
T128 |
180077 |
462 |
0 |
0 |
T132 |
8449 |
7 |
0 |
0 |
T155 |
3691 |
4 |
0 |
0 |
T156 |
5561 |
10 |
0 |
0 |
T157 |
11723 |
17 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
6115 |
0 |
0 |
T85 |
3194 |
9 |
0 |
0 |
T103 |
98439 |
858 |
0 |
0 |
T117 |
10784 |
14 |
0 |
0 |
T118 |
6106 |
5 |
0 |
0 |
T119 |
9601 |
28 |
0 |
0 |
T122 |
3641 |
1 |
0 |
0 |
T128 |
180077 |
482 |
0 |
0 |
T132 |
8449 |
5 |
0 |
0 |
T155 |
3691 |
9 |
0 |
0 |
T156 |
5561 |
5 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
6335 |
0 |
0 |
T85 |
3194 |
6 |
0 |
0 |
T103 |
98439 |
875 |
0 |
0 |
T117 |
10784 |
45 |
0 |
0 |
T118 |
6106 |
5 |
0 |
0 |
T119 |
9601 |
35 |
0 |
0 |
T122 |
3641 |
42 |
0 |
0 |
T128 |
180077 |
462 |
0 |
0 |
T132 |
8449 |
58 |
0 |
0 |
T155 |
3691 |
3 |
0 |
0 |
T156 |
5561 |
8 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
2919 |
0 |
0 |
T103 |
98439 |
138 |
0 |
0 |
T117 |
10784 |
26 |
0 |
0 |
T118 |
6106 |
2 |
0 |
0 |
T128 |
180077 |
456 |
0 |
0 |
T132 |
8449 |
17 |
0 |
0 |
T155 |
3691 |
9 |
0 |
0 |
T156 |
5561 |
2 |
0 |
0 |
T157 |
11723 |
14 |
0 |
0 |
T158 |
14761 |
26 |
0 |
0 |
T159 |
6473 |
10 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
3042 |
0 |
0 |
T85 |
3194 |
2 |
0 |
0 |
T103 |
98439 |
126 |
0 |
0 |
T117 |
10784 |
17 |
0 |
0 |
T118 |
6106 |
9 |
0 |
0 |
T119 |
9601 |
14 |
0 |
0 |
T128 |
180077 |
377 |
0 |
0 |
T132 |
8449 |
8 |
0 |
0 |
T155 |
3691 |
5 |
0 |
0 |
T156 |
5561 |
11 |
0 |
0 |
T157 |
11723 |
28 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
2897 |
0 |
0 |
T85 |
3194 |
13 |
0 |
0 |
T103 |
98439 |
145 |
0 |
0 |
T117 |
10784 |
11 |
0 |
0 |
T118 |
6106 |
12 |
0 |
0 |
T122 |
3641 |
5 |
0 |
0 |
T128 |
180077 |
413 |
0 |
0 |
T132 |
8449 |
14 |
0 |
0 |
T156 |
5561 |
13 |
0 |
0 |
T157 |
11723 |
10 |
0 |
0 |
T158 |
14761 |
24 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
2996 |
0 |
0 |
T85 |
3194 |
9 |
0 |
0 |
T103 |
98439 |
141 |
0 |
0 |
T117 |
10784 |
20 |
0 |
0 |
T118 |
6106 |
17 |
0 |
0 |
T119 |
9601 |
14 |
0 |
0 |
T122 |
3641 |
9 |
0 |
0 |
T128 |
180077 |
421 |
0 |
0 |
T132 |
8449 |
12 |
0 |
0 |
T155 |
3691 |
7 |
0 |
0 |
T156 |
5561 |
9 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
3549 |
0 |
0 |
T103 |
98439 |
319 |
0 |
0 |
T117 |
10784 |
24 |
0 |
0 |
T118 |
6106 |
26 |
0 |
0 |
T119 |
9601 |
7 |
0 |
0 |
T122 |
3641 |
3 |
0 |
0 |
T128 |
180077 |
388 |
0 |
0 |
T132 |
8449 |
18 |
0 |
0 |
T155 |
3691 |
15 |
0 |
0 |
T156 |
5561 |
9 |
0 |
0 |
T157 |
11723 |
19 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
5085 |
0 |
0 |
T20 |
7230 |
43 |
0 |
0 |
T21 |
4090 |
0 |
0 |
0 |
T22 |
0 |
41 |
0 |
0 |
T23 |
0 |
32 |
0 |
0 |
T80 |
167925 |
0 |
0 |
0 |
T81 |
178799 |
0 |
0 |
0 |
T152 |
28468 |
0 |
0 |
0 |
T160 |
0 |
28 |
0 |
0 |
T161 |
0 |
20 |
0 |
0 |
T162 |
0 |
16 |
0 |
0 |
T163 |
0 |
32 |
0 |
0 |
T164 |
0 |
29 |
0 |
0 |
T165 |
0 |
23 |
0 |
0 |
T166 |
0 |
71 |
0 |
0 |
T167 |
168368 |
0 |
0 |
0 |
T168 |
10649 |
0 |
0 |
0 |
T169 |
245309 |
0 |
0 |
0 |
T170 |
446021 |
0 |
0 |
0 |
T171 |
115066 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
3076 |
0 |
0 |
T85 |
3194 |
5 |
0 |
0 |
T103 |
98439 |
212 |
0 |
0 |
T117 |
10784 |
24 |
0 |
0 |
T118 |
6106 |
11 |
0 |
0 |
T119 |
9601 |
5 |
0 |
0 |
T122 |
3641 |
2 |
0 |
0 |
T128 |
180077 |
395 |
0 |
0 |
T132 |
8449 |
9 |
0 |
0 |
T155 |
3691 |
6 |
0 |
0 |
T156 |
5561 |
20 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
2971 |
0 |
0 |
T85 |
3194 |
5 |
0 |
0 |
T103 |
98439 |
151 |
0 |
0 |
T117 |
10784 |
13 |
0 |
0 |
T118 |
6106 |
19 |
0 |
0 |
T119 |
9601 |
7 |
0 |
0 |
T122 |
3641 |
8 |
0 |
0 |
T128 |
180077 |
412 |
0 |
0 |
T132 |
8449 |
17 |
0 |
0 |
T155 |
3691 |
5 |
0 |
0 |
T156 |
5561 |
21 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
2739 |
0 |
0 |
T85 |
3194 |
4 |
0 |
0 |
T103 |
98439 |
119 |
0 |
0 |
T117 |
10784 |
15 |
0 |
0 |
T118 |
6106 |
7 |
0 |
0 |
T119 |
9601 |
11 |
0 |
0 |
T122 |
3641 |
4 |
0 |
0 |
T128 |
180077 |
439 |
0 |
0 |
T132 |
8449 |
18 |
0 |
0 |
T155 |
3691 |
1 |
0 |
0 |
T156 |
5561 |
10 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
2860 |
0 |
0 |
T85 |
3194 |
4 |
0 |
0 |
T103 |
98439 |
130 |
0 |
0 |
T117 |
10784 |
19 |
0 |
0 |
T118 |
6106 |
2 |
0 |
0 |
T119 |
9601 |
11 |
0 |
0 |
T122 |
3641 |
3 |
0 |
0 |
T128 |
180077 |
434 |
0 |
0 |
T132 |
8449 |
1 |
0 |
0 |
T155 |
3691 |
3 |
0 |
0 |
T156 |
5561 |
7 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
2754 |
0 |
0 |
T85 |
3194 |
3 |
0 |
0 |
T103 |
98439 |
122 |
0 |
0 |
T117 |
10784 |
9 |
0 |
0 |
T118 |
6106 |
9 |
0 |
0 |
T119 |
9601 |
6 |
0 |
0 |
T128 |
180077 |
496 |
0 |
0 |
T132 |
8449 |
11 |
0 |
0 |
T155 |
3691 |
7 |
0 |
0 |
T156 |
5561 |
6 |
0 |
0 |
T157 |
11723 |
20 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
2776 |
0 |
0 |
T103 |
98439 |
119 |
0 |
0 |
T117 |
10784 |
19 |
0 |
0 |
T118 |
6106 |
8 |
0 |
0 |
T119 |
9601 |
6 |
0 |
0 |
T128 |
180077 |
453 |
0 |
0 |
T132 |
8449 |
15 |
0 |
0 |
T155 |
3691 |
8 |
0 |
0 |
T157 |
11723 |
11 |
0 |
0 |
T158 |
14761 |
25 |
0 |
0 |
T172 |
271564 |
687 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
3568 |
0 |
0 |
T85 |
3194 |
9 |
0 |
0 |
T103 |
98439 |
310 |
0 |
0 |
T117 |
10784 |
9 |
0 |
0 |
T118 |
6106 |
17 |
0 |
0 |
T119 |
9601 |
11 |
0 |
0 |
T122 |
3641 |
22 |
0 |
0 |
T128 |
180077 |
470 |
0 |
0 |
T132 |
8449 |
7 |
0 |
0 |
T155 |
3691 |
25 |
0 |
0 |
T156 |
5561 |
12 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
2657 |
0 |
0 |
T85 |
3194 |
7 |
0 |
0 |
T103 |
98439 |
143 |
0 |
0 |
T117 |
10784 |
23 |
0 |
0 |
T118 |
6106 |
13 |
0 |
0 |
T119 |
9601 |
2 |
0 |
0 |
T122 |
3641 |
5 |
0 |
0 |
T128 |
180077 |
396 |
0 |
0 |
T132 |
8449 |
11 |
0 |
0 |
T155 |
3691 |
9 |
0 |
0 |
T156 |
5561 |
1 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
4008 |
0 |
0 |
T85 |
3194 |
2 |
0 |
0 |
T103 |
98439 |
296 |
0 |
0 |
T117 |
10784 |
49 |
0 |
0 |
T118 |
6106 |
35 |
0 |
0 |
T119 |
9601 |
14 |
0 |
0 |
T122 |
3641 |
13 |
0 |
0 |
T128 |
180077 |
498 |
0 |
0 |
T132 |
8449 |
18 |
0 |
0 |
T155 |
3691 |
2 |
0 |
0 |
T156 |
5561 |
25 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
3034 |
0 |
0 |
T85 |
3194 |
12 |
0 |
0 |
T103 |
98439 |
130 |
0 |
0 |
T117 |
10784 |
22 |
0 |
0 |
T118 |
6106 |
6 |
0 |
0 |
T119 |
9601 |
8 |
0 |
0 |
T128 |
180077 |
465 |
0 |
0 |
T132 |
8449 |
18 |
0 |
0 |
T155 |
3691 |
5 |
0 |
0 |
T156 |
5561 |
12 |
0 |
0 |
T157 |
11723 |
13 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
2686 |
0 |
0 |
T85 |
3194 |
14 |
0 |
0 |
T103 |
98439 |
126 |
0 |
0 |
T117 |
10784 |
16 |
0 |
0 |
T118 |
6106 |
9 |
0 |
0 |
T119 |
9601 |
5 |
0 |
0 |
T128 |
180077 |
403 |
0 |
0 |
T155 |
3691 |
10 |
0 |
0 |
T156 |
5561 |
3 |
0 |
0 |
T157 |
11723 |
11 |
0 |
0 |
T158 |
14761 |
39 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
2573 |
0 |
0 |
T85 |
3194 |
3 |
0 |
0 |
T103 |
98439 |
132 |
0 |
0 |
T117 |
10784 |
11 |
0 |
0 |
T118 |
6106 |
12 |
0 |
0 |
T119 |
9601 |
2 |
0 |
0 |
T128 |
180077 |
432 |
0 |
0 |
T132 |
8449 |
11 |
0 |
0 |
T155 |
3691 |
3 |
0 |
0 |
T156 |
5561 |
10 |
0 |
0 |
T157 |
11723 |
6 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
2708 |
0 |
0 |
T85 |
3194 |
6 |
0 |
0 |
T103 |
98439 |
131 |
0 |
0 |
T117 |
10784 |
20 |
0 |
0 |
T118 |
6106 |
12 |
0 |
0 |
T119 |
9601 |
14 |
0 |
0 |
T122 |
3641 |
6 |
0 |
0 |
T128 |
180077 |
425 |
0 |
0 |
T132 |
8449 |
11 |
0 |
0 |
T155 |
3691 |
3 |
0 |
0 |
T156 |
5561 |
3 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
2698 |
0 |
0 |
T85 |
3194 |
10 |
0 |
0 |
T103 |
98439 |
117 |
0 |
0 |
T117 |
10784 |
7 |
0 |
0 |
T118 |
6106 |
9 |
0 |
0 |
T119 |
9601 |
7 |
0 |
0 |
T122 |
3641 |
5 |
0 |
0 |
T128 |
180077 |
425 |
0 |
0 |
T132 |
8449 |
10 |
0 |
0 |
T155 |
3691 |
6 |
0 |
0 |
T156 |
5561 |
7 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
2686 |
0 |
0 |
T85 |
3194 |
13 |
0 |
0 |
T103 |
98439 |
94 |
0 |
0 |
T117 |
10784 |
11 |
0 |
0 |
T118 |
6106 |
18 |
0 |
0 |
T119 |
9601 |
19 |
0 |
0 |
T128 |
180077 |
462 |
0 |
0 |
T132 |
8449 |
9 |
0 |
0 |
T155 |
3691 |
4 |
0 |
0 |
T156 |
5561 |
14 |
0 |
0 |
T157 |
11723 |
4 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
445940439 |
2587 |
0 |
0 |
T85 |
3194 |
5 |
0 |
0 |
T103 |
98439 |
103 |
0 |
0 |
T117 |
10784 |
17 |
0 |
0 |
T118 |
6106 |
3 |
0 |
0 |
T119 |
9601 |
12 |
0 |
0 |
T128 |
180077 |
416 |
0 |
0 |
T156 |
5561 |
1 |
0 |
0 |
T157 |
11723 |
16 |
0 |
0 |
T158 |
14761 |
27 |
0 |
0 |
T159 |
6473 |
12 |
0 |
0 |