Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3676121	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4356680

1

T1

1653

T2

83

T3

6647

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4443349	1			T1	1610		T2	1		T3	3923
values[0x0]	1791594	1			T1	462		T2	53		T3	3106
values[0x1]	1797858	1			T1	416		T2	54		T3	3220

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2611435	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5421366

1

T1

1835

T2

91

T3

7639

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	32166	1			T1	13		T3	51		T4	19
valid_sources[0x01]	29937	1			T3	43		T4	40		T6	4
valid_sources[0x02]	30811	1			T1	2		T3	41		T4	30
valid_sources[0x03]	30724	1			T1	6		T2	2		T3	29
valid_sources[0x04]	29033	1			T1	8		T3	28		T4	31
valid_sources[0x05]	28799	1			T1	6		T3	20		T4	30
valid_sources[0x06]	32405	1			T1	24		T3	71		T4	22
valid_sources[0x07]	29838	1			T1	13		T2	5		T3	50
valid_sources[0x08]	30456	1			T1	4		T3	44		T4	33
valid_sources[0x09]	31986	1			T1	9		T2	1		T3	65
valid_sources[0x0a]	27883	1			T1	16		T3	83		T4	26
valid_sources[0x0b]	30740	1			T1	13		T3	14		T4	32
valid_sources[0x0c]	36469	1			T1	8		T2	3		T3	31
valid_sources[0x0d]	28693	1			T1	15		T3	24		T4	25
valid_sources[0x0e]	39909	1			T1	5		T3	61		T4	23
valid_sources[0x0f]	31426	1			T1	13		T3	56		T4	22
valid_sources[0x10]	29480	1			T1	25		T2	1		T3	66
valid_sources[0x11]	35240	1			T1	1		T3	20		T4	26
valid_sources[0x12]	29089	1			T1	3		T3	46		T4	19
valid_sources[0x13]	30535	1			T1	7		T3	29		T4	31
valid_sources[0x14]	29561	1			T1	34		T3	44		T4	9
valid_sources[0x15]	28659	1			T1	5		T3	32		T4	35
valid_sources[0x16]	34078	1			T3	28		T4	26		T6	5
valid_sources[0x17]	29866	1			T1	31		T3	23		T4	32
valid_sources[0x18]	32188	1			T1	3		T3	60		T4	28
valid_sources[0x19]	31718	1			T1	17		T3	24		T4	29
valid_sources[0x1a]	28056	1			T1	4		T3	41		T4	30
valid_sources[0x1b]	29440	1			T1	5		T3	37		T4	33
valid_sources[0x1c]	30621	1			T1	3		T3	18		T4	38
valid_sources[0x1d]	32924	1			T1	21		T3	33		T4	29
valid_sources[0x1e]	29504	1			T1	6		T3	27		T4	25
valid_sources[0x1f]	29202	1			T2	2		T3	47		T4	22
valid_sources[0x20]	30271	1			T1	27		T3	34		T4	33
valid_sources[0x21]	28386	1			T1	2		T2	1		T3	24
valid_sources[0x22]	31758	1			T3	48		T4	32		T6	3
valid_sources[0x23]	30499	1			T1	1		T3	77		T4	45
valid_sources[0x24]	30455	1			T1	8		T3	56		T4	19
valid_sources[0x25]	35683	1			T3	47		T4	36		T6	10
valid_sources[0x26]	30210	1			T1	9		T2	6		T3	84
valid_sources[0x27]	29652	1			T3	35		T4	27		T6	7
valid_sources[0x28]	29117	1			T3	69		T4	20		T6	4
valid_sources[0x29]	31284	1			T1	3		T3	46		T4	20
valid_sources[0x2a]	30367	1			T1	9		T3	19		T4	28
valid_sources[0x2b]	31328	1			T1	17		T3	53		T4	29
valid_sources[0x2c]	27620	1			T1	17		T3	44		T4	21
valid_sources[0x2d]	30222	1			T1	8		T3	54		T4	26
valid_sources[0x2e]	31097	1			T1	3		T3	16		T4	26
valid_sources[0x2f]	30117	1			T1	27		T3	28		T4	29
valid_sources[0x30]	30571	1			T1	10		T3	46		T4	28
valid_sources[0x31]	37990	1			T2	3		T3	35		T4	20
valid_sources[0x32]	30702	1			T1	1		T3	49		T4	28
valid_sources[0x33]	29264	1			T1	17		T3	37		T4	47
valid_sources[0x34]	32017	1			T1	1		T2	5		T3	39
valid_sources[0x35]	31399	1			T3	29		T4	21		T6	5
valid_sources[0x36]	32072	1			T1	3		T2	1		T3	32
valid_sources[0x37]	28911	1			T1	7		T3	68		T4	23
valid_sources[0x38]	27026	1			T1	7		T3	35		T4	30
valid_sources[0x39]	28477	1			T1	2		T3	30		T4	32
valid_sources[0x3a]	31026	1			T1	9		T3	82		T4	29
valid_sources[0x3b]	29218	1			T1	9		T2	1		T3	61
valid_sources[0x3c]	29058	1			T1	10		T3	33		T4	20
valid_sources[0x3d]	29625	1			T1	2		T3	78		T4	36
valid_sources[0x3e]	30442	1			T1	19		T3	31		T4	24
valid_sources[0x3f]	30246	1			T1	9		T3	33		T4	26
valid_sources[0x40]	31851	1			T1	6		T3	54		T4	34
valid_sources[0x41]	54537	1			T1	22		T2	5		T3	51
valid_sources[0x42]	29994	1			T1	10		T2	9		T3	46
valid_sources[0x43]	31638	1			T1	28		T3	46		T4	29
valid_sources[0x44]	32765	1			T1	9		T3	60		T4	25
valid_sources[0x45]	29553	1			T1	4		T3	71		T4	30
valid_sources[0x46]	28948	1			T1	1		T3	47		T4	26
valid_sources[0x47]	29932	1			T1	15		T3	44		T4	33
valid_sources[0x48]	28820	1			T1	11		T3	57		T4	33
valid_sources[0x49]	29806	1			T1	5		T2	1		T3	41
valid_sources[0x4a]	34840	1			T1	7		T3	32		T4	25
valid_sources[0x4b]	28620	1			T1	4		T3	54		T4	34
valid_sources[0x4c]	32655	1			T3	30		T4	24		T6	5
valid_sources[0x4d]	30795	1			T1	9		T3	48		T4	25
valid_sources[0x4e]	31638	1			T3	22		T4	38		T6	4
valid_sources[0x4f]	38491	1			T1	5		T3	34		T4	41
valid_sources[0x50]	34318	1			T1	1		T3	45		T4	27
valid_sources[0x51]	31354	1			T1	5		T3	41		T4	30
valid_sources[0x52]	30309	1			T1	40		T3	37		T4	35
valid_sources[0x53]	31598	1			T1	9		T3	44		T4	23
valid_sources[0x54]	50051	1			T1	4		T3	52		T4	17
valid_sources[0x55]	42169	1			T3	28		T4	32		T6	5
valid_sources[0x56]	31668	1			T3	62		T4	28		T6	3
valid_sources[0x57]	31264	1			T1	12		T3	17		T4	23
valid_sources[0x58]	30032	1			T3	26		T4	33		T6	2
valid_sources[0x59]	30344	1			T1	3		T2	1		T3	20
valid_sources[0x5a]	28664	1			T1	2		T3	35		T4	36
valid_sources[0x5b]	29240	1			T1	9		T3	27		T4	40
valid_sources[0x5c]	29069	1			T1	4		T3	42		T4	37
valid_sources[0x5d]	28708	1			T1	6		T3	45		T4	38
valid_sources[0x5e]	36081	1			T1	28		T3	60		T4	29
valid_sources[0x5f]	30982	1			T1	21		T3	56		T4	32
valid_sources[0x60]	33514	1			T3	20		T4	27		T6	3
valid_sources[0x61]	29787	1			T2	2		T3	40		T4	44
valid_sources[0x62]	34336	1			T1	5		T3	44		T4	40
valid_sources[0x63]	29542	1			T1	3		T3	50		T4	25
valid_sources[0x64]	28219	1			T3	54		T4	21		T6	6
valid_sources[0x65]	37731	1			T1	10		T3	27		T4	34
valid_sources[0x66]	31513	1			T1	10		T3	60		T4	33
valid_sources[0x67]	30425	1			T3	34		T4	26		T6	4
valid_sources[0x68]	31623	1			T1	1		T3	51		T4	22
valid_sources[0x69]	29760	1			T1	2		T3	36		T4	43
valid_sources[0x6a]	30714	1			T1	12		T2	2		T3	24
valid_sources[0x6b]	32477	1			T1	4		T3	38		T4	28
valid_sources[0x6c]	29764	1			T1	17		T3	41		T4	22
valid_sources[0x6d]	33459	1			T1	12		T3	63		T4	28
valid_sources[0x6e]	31283	1			T1	32		T3	46		T4	39
valid_sources[0x6f]	29259	1			T1	18		T2	3		T3	34
valid_sources[0x70]	30890	1			T1	29		T3	16		T4	35
valid_sources[0x71]	32077	1			T1	4		T3	52		T4	36
valid_sources[0x72]	30840	1			T1	8		T3	34		T4	32
valid_sources[0x73]	31189	1			T1	36		T2	2		T3	51
valid_sources[0x74]	29430	1			T1	9		T3	32		T4	30
valid_sources[0x75]	33400	1			T1	5		T3	40		T4	22
valid_sources[0x76]	31232	1			T1	1		T2	2		T3	19
valid_sources[0x77]	28937	1			T1	6		T3	48		T4	23
valid_sources[0x78]	30851	1			T1	6		T3	36		T4	23
valid_sources[0x79]	30378	1			T1	6		T3	35		T4	36
valid_sources[0x7a]	30270	1			T1	10		T2	2		T3	36
valid_sources[0x7b]	30941	1			T1	33		T3	39		T4	24
valid_sources[0x7c]	29734	1			T1	10		T3	43		T4	15
valid_sources[0x7d]	28976	1			T1	6		T3	81		T4	36
valid_sources[0x7e]	33410	1			T3	56		T4	28		T6	6
valid_sources[0x7f]	28537	1			T1	18		T3	46		T4	40
valid_sources[0x80]	28833	1			T1	9		T3	52		T4	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1105429

1

T1

777

T3

1263

T4

1158

values[0x0]

all_enables

biggest_size

1635798

1

T1

461

T2

43

T3

2667

values[0x1]

all_enables

biggest_size

1615453

1

T1

415

T2

40

T3

2717