Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3697671

1

T1

835

T2

25

T3

3602

full_word

4355910

1

T1

1653

T2

83

T3

6647

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8053141	1			T1	2488		T2	108		T3	10249
auto[TlIntgErrCmd]	161	1			T91	8		T92	9		T93	4
auto[TlIntgErrData]	136	1			T91	5		T92	11		T93	5
auto[TlIntgErrBoth]	143	1			T91	7		T92	10		T93	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4446206

1

T1

1610

T2

1

T3

3923

auto[1]

3607375

1

T1

878

T2

107

T3

6326

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3340425	1			T1	833		T2	1		T3	2660
auto[TlIntgErrNone]	partial	auto[1]	356843	1			T1	2		T2	24		T3	942
auto[TlIntgErrNone]	full_word	auto[0]	1105576	1			T1	777		T3	1263		T4	1158
auto[TlIntgErrNone]	full_word	auto[1]	3250297	1			T1	876		T2	83		T3	5384
auto[TlIntgErrCmd]	partial	auto[0]	58	1			T91	3		T92	1		T113	1
auto[TlIntgErrCmd]	partial	auto[1]	85	1			T91	5		T92	8		T93	4
auto[TlIntgErrCmd]	full_word	auto[0]	11	1			T114	1		T171	1		T108	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T113	1		T112	1		T170	2
auto[TlIntgErrData]	partial	auto[0]	77	1			T91	2		T92	5		T93	3
auto[TlIntgErrData]	partial	auto[1]	50	1			T91	3		T92	3		T93	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T92	3		T114	1		T112	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T172	1		T173	1		T174	1
auto[TlIntgErrBoth]	partial	auto[0]	51	1			T91	3		T92	5		T93	1
auto[TlIntgErrBoth]	partial	auto[1]	82	1			T91	4		T92	5		T113	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T112	1		T173	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T112	1		T170	3		T172	1