Unified Coverage Report :: Module Instance :: tb.dut.u_tlul2sram_egress.u_rspfifo

Module Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.67	86.67	33.33			66.67	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.36	85.00	45.45			55.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.14	94.52	60.33			73.08	84.62	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	63.15	84.00	60.00			45.45

Module Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.76	94.52	71.90			84.62	100.00	u_tlul2sram_ingress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.64	95.00	72.22			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.76	94.52	71.90			84.62	100.00	u_tlul2sram_ingress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.32	95.00	77.27			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.76	94.52	71.90			84.62	100.00	u_tlul2sram_ingress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.06	100.00	56.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	100.00	75.00			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	93.64	100.00	90.00			90.91

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	13	86.67
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	1	50.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	0	1
111	1	1
112	0	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Total	Covered	Percent
Conditions	24	8	33.33
Logical	24	8	33.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	6	66.67
TERNARY	130	2	1	50.00
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	111	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457208051	0	0	0
DepthKnown_A	457208051	457120622	0	0
RvalidKnown_A	457208051	457120622	0	0
WreadyKnown_A	457208051	457120622	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	457208051	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	457120622	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	457120622	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	457120622	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	0	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T4,T8
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T8

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T3,T4,T8
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457208051	474177	0	0
DepthKnown_A	457208051	457120622	0	0
RvalidKnown_A	457208051	457120622	0	0
WreadyKnown_A	457208051	457120622	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	457208051	474177	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	474177	0	0
T3	216902	2988	0	0
T4	125057	1125	0	0
T5	9202	0	0	0
T6	17048	0	0	0
T7	131090	0	0	0
T8	336150	1613	0	0
T9	1066	0	0	0
T10	332648	1855	0	0
T11	88290	0	0	0
T12	182409	0	0	0
T13	0	257	0	0
T31	0	245	0	0
T32	0	2838	0	0
T33	0	1198	0	0
T36	0	1827	0	0
T48	0	905	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	457120622	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	457120622	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	457120622	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	474177	0	0
T3	216902	2988	0	0
T4	125057	1125	0	0
T5	9202	0	0	0
T6	17048	0	0	0
T7	131090	0	0	0
T8	336150	1613	0	0
T9	1066	0	0	0
T10	332648	1855	0	0
T11	88290	0	0	0
T12	182409	0	0	0
T13	0	257	0	0
T31	0	245	0	0
T32	0	2838	0	0
T33	0	1198	0	0
T36	0	1827	0	0
T48	0	905	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T8

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T3,T4,T8
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457208051	180441	0	0
DepthKnown_A	457208051	457120622	0	0
RvalidKnown_A	457208051	457120622	0	0
WreadyKnown_A	457208051	457120622	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	457208051	180441	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	180441	0	0
T3	216902	982	0	0
T4	125057	256	0	0
T5	9202	0	0	0
T6	17048	0	0	0
T7	131090	0	0	0
T8	336150	540	0	0
T9	1066	0	0	0
T10	332648	418	0	0
T11	88290	0	0	0
T12	182409	0	0	0
T13	0	257	0	0
T31	0	245	0	0
T32	0	616	0	0
T33	0	1198	0	0
T36	0	403	0	0
T48	0	192	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	457120622	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	457120622	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	457120622	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	180441	0	0
T3	216902	982	0	0
T4	125057	256	0	0
T5	9202	0	0	0
T6	17048	0	0	0
T7	131090	0	0	0
T8	336150	540	0	0
T9	1066	0	0	0
T10	332648	418	0	0
T11	88290	0	0	0
T12	182409	0	0	0
T13	0	257	0	0
T31	0	245	0	0
T32	0	616	0	0
T33	0	1198	0	0
T36	0	403	0	0
T48	0	192	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T4,T8
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T8

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T8

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T8

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T8
1	0	Covered	T3,T4,T8
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T3,T4,T8
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457208051	474177	0	0
DepthKnown_A	457208051	457120622	0	0
RvalidKnown_A	457208051	457120622	0	0
WreadyKnown_A	457208051	457120622	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	457208051	474177	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	474177	0	0
T3	216902	2988	0	0
T4	125057	1125	0	0
T5	9202	0	0	0
T6	17048	0	0	0
T7	131090	0	0	0
T8	336150	1613	0	0
T9	1066	0	0	0
T10	332648	1855	0	0
T11	88290	0	0	0
T12	182409	0	0	0
T13	0	257	0	0
T31	0	245	0	0
T32	0	2838	0	0
T33	0	1198	0	0
T36	0	1827	0	0
T48	0	905	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	457120622	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	457120622	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	457120622	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	474177	0	0
T3	216902	2988	0	0
T4	125057	1125	0	0
T5	9202	0	0	0
T6	17048	0	0	0
T7	131090	0	0	0
T8	336150	1613	0	0
T9	1066	0	0	0
T10	332648	1855	0	0
T11	88290	0	0	0
T12	182409	0	0	0
T13	0	257	0	0
T31	0	245	0	0
T32	0	2838	0	0
T33	0	1198	0	0
T36	0	1827	0	0
T48	0	905	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	16	9	56.25
Logical	16	9	56.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T8

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T3,T4,T8
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457208051	184420	0	0
DepthKnown_A	457208051	457120622	0	0
RvalidKnown_A	457208051	457120622	0	0
WreadyKnown_A	457208051	457120622	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	457208051	184420	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	184420	0	0
T3	216902	986	0	0
T4	125057	262	0	0
T5	9202	0	0	0
T6	17048	0	0	0
T7	131090	0	0	0
T8	336150	561	0	0
T9	1066	0	0	0
T10	332648	449	0	0
T11	88290	0	0	0
T12	182409	0	0	0
T13	0	268	0	0
T31	0	246	0	0
T32	0	622	0	0
T33	0	1238	0	0
T48	0	200	0	0
T54	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	457120622	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	457120622	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	457120622	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	457208051	184420	0	0
T3	216902	986	0	0
T4	125057	262	0	0
T5	9202	0	0	0
T6	17048	0	0	0
T7	131090	0	0	0
T8	336150	561	0	0
T9	1066	0	0	0
T10	332648	449	0	0
T11	88290	0	0	0
T12	182409	0	0	0
T13	0	268	0	0
T31	0	246	0	0
T32	0	622	0	0
T33	0	1238	0	0
T48	0	200	0	0
T54	0	4	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	459927526	9679934	0	0
DepthKnown_A	459927526	459792793	0	0
RvalidKnown_A	459927526	459792793	0	0
WreadyKnown_A	459927526	459792793	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	9679934	0	0
T1	29267	2488	0	0
T2	76256	108	0	0
T3	216902	12552	0	0
T4	125057	10786	0	0
T5	9202	896	0	0
T6	17048	1252	0	0
T7	131090	1947	0	0
T8	336150	13544	0	0
T9	1066	12	0	0
T10	332648	16842	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	459792793	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	459792793	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	459792793	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	459927526	18425121	0	0
DepthKnown_A	459927526	459792793	0	0
RvalidKnown_A	459927526	459792793	0	0
WreadyKnown_A	459927526	459792793	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	18425121	0	0
T1	29267	2488	0	0
T2	76256	108	0	0
T3	216902	30125	0	0
T4	125057	21384	0	0
T5	9202	894	0	0
T6	17048	1252	0	0
T7	131090	2070	0	0
T8	336150	28790	0	0
T9	1066	12	0	0
T10	332648	53212	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	459792793	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	459792793	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	459792793	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0