Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	459927526	2888691	0	0
DepthKnown_A	459927526	459792793	0	0
RvalidKnown_A	459927526	459792793	0	0
WreadyKnown_A	459927526	459792793	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	2888691	0	0
T1	29267	832	0	0
T2	76256	0	0	0
T3	216902	3328	0	0
T4	125057	8336	0	0
T5	9202	832	0	0
T6	17048	832	0	0
T7	131090	1668	0	0
T8	336150	8317	0	0
T9	1066	0	0	0
T10	332648	10829	0	0
T11	0	832	0	0
T12	0	1669	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	459792793	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	459792793	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	459792793	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	459927526	3300989	0	0
DepthKnown_A	459927526	459792793	0	0
RvalidKnown_A	459927526	459792793	0	0
WreadyKnown_A	459927526	459792793	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	3300989	0	0
T1	29267	832	0	0
T2	76256	0	0	0
T3	216902	5904	0	0
T4	125057	10855	0	0
T5	9202	832	0	0
T6	17048	832	0	0
T7	131090	837	0	0
T8	336150	12768	0	0
T9	1066	0	0	0
T10	332648	28488	0	0
T11	0	832	0	0
T12	0	839	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	459792793	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	459792793	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	459792793	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	459927526	195433	0	0
DepthKnown_A	459927526	459792793	0	0
RvalidKnown_A	459927526	459792793	0	0
WreadyKnown_A	459927526	459792793	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	195433	0	0
T3	216902	982	0	0
T4	125057	256	0	0
T5	9202	0	0	0
T6	17048	0	0	0
T7	131090	0	0	0
T8	336150	540	0	0
T9	1066	0	0	0
T10	332648	418	0	0
T11	88290	0	0	0
T12	182409	0	0	0
T13	0	257	0	0
T31	0	245	0	0
T32	0	638	0	0
T33	0	1199	0	0
T36	0	403	0	0
T48	0	192	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	459792793	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	459792793	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	459792793	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	459927526	487324	0	0
DepthKnown_A	459927526	459792793	0	0
RvalidKnown_A	459927526	459792793	0	0
WreadyKnown_A	459927526	459792793	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	487324	0	0
T3	216902	2988	0	0
T4	125057	1125	0	0
T5	9202	0	0	0
T6	17048	0	0	0
T7	131090	0	0	0
T8	336150	1613	0	0
T9	1066	0	0	0
T10	332648	1855	0	0
T11	88290	0	0	0
T12	182409	0	0	0
T13	0	257	0	0
T31	0	245	0	0
T32	0	2838	0	0
T33	0	1198	0	0
T36	0	1827	0	0
T48	0	905	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	459792793	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	459792793	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	459792793	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	459927526	6393296	0	0
DepthKnown_A	459927526	459792793	0	0
RvalidKnown_A	459927526	459792793	0	0
WreadyKnown_A	459927526	459792793	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	6393296	0	0
T1	29267	1656	0	0
T2	76256	108	0	0
T3	216902	7197	0	0
T4	125057	2164	0	0
T5	9202	62	0	0
T6	17048	420	0	0
T7	131090	279	0	0
T8	336150	4590	0	0
T9	1066	12	0	0
T10	332648	5291	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	459792793	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	459792793	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	459792793	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	459927526	14636808	0	0
DepthKnown_A	459927526	459792793	0	0
RvalidKnown_A	459927526	459792793	0	0
WreadyKnown_A	459927526	459792793	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	14636808	0	0
T1	29267	1656	0	0
T2	76256	108	0	0
T3	216902	21233	0	0
T4	125057	9404	0	0
T5	9202	62	0	0
T6	17048	420	0	0
T7	131090	1233	0	0
T8	336150	14409	0	0
T9	1066	12	0	0
T10	332648	22869	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	459792793	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	459792793	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459927526	459792793	0	0
T1	29267	29185	0	0
T2	76256	76161	0	0
T3	216902	216829	0	0
T4	125057	125051	0	0
T5	9202	9134	0	0
T6	17048	16994	0	0
T7	131090	131013	0	0
T8	336150	336140	0	0
T9	1066	991	0	0
T10	332648	332638	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0